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SM-4.2 Desain Rangkaian Sekuensial
SM-4.2 Desain Rangkaian Sekuensial
(Sekuensial)
Fajar Budiman
Analisa Rangkaian Sekuensial
Analisa Rangkaian Digital
Desain Rangkaian Digital
Memory
Analisa Rangkaian Sekuensial
Analisa Rangkaian Sekuensial
Dinyatakan dengan state equation (secara boolean algebra)
State equation disebut juga transition equation
Menentukan next state sebagai sebuah fungsi present state
dan input
Analisa Rangkaian Sekuensial
Analisa Rangkaian Sekuensial
State table (transition table)
Pada umumnya: m flip-flop dan n input membutuhkan
sebanyak 2m+n baris, dan sebanyak m kolom untuk next state
(1 untuk 1 flip-flop)
Analisa Rangkaian Sekuensial
State diagram
Analisa Rangkaian
Input / Output2Output1Output0
Present State = sn
Input = xn
Output = zn
Truth Table for the s1 s0 x1 x0 s1 s0 z2 z1 z0
0 0 0 0 0 0 1 0 0 0
Vending Machine 1 0 0 0 1 1 0 0 0 0
2 0 0 1 0 0 0 1 1 0
3 0 0 1 1 d d d d d
4 0 1 0 0 1 0 0 0 0
5 0 1 0 1 1 1 0 0 0
For the FSM circuit, we will need: 6 0 1 1 0 0 0 1 0 1
7 0 1 1 1 d d d d d
Two D flip-flops to represent the two
state bits. 8 1 0 0 0 1 1 0 0 0
9 1 0 0 1 0 0 1 0 0
PLA that takes four inputs (two for the 10 1 0 1 0 0 0 1 0 0
present state bits and two for the coin
11 1 0 1 1 d d d d d
bits) and has five outputs (two for the
next state bits and three for the dispense 12 1 1 0 0 0 0 1 1 1
and return bits). 13 1 1 0 1 0 0 1 1 0
14 1 1 1 0 0 1 1 1 1
15 1 1 1 1 d d d d d
Logic Design for the Vending
Machine
x1 z2
x0 z1
5x5 z0
PLA
Assumes the clock input is asserted only
on an event such as the user inserting a
coin into the machine.
Q D
s0
CLK
Q D
s1