Professional Documents
Culture Documents
Delays in Verilog: Presented BY: Jitu Mistry
Delays in Verilog: Presented BY: Jitu Mistry
Delays in Verilog: Presented BY: Jitu Mistry
Presented BY:
Jitu Mistry
7/30/2013
Types of Delays.
3
Gate-level Modeling
Dataflow Modeling
Behavioral Modeling
7/19/2013
Gate level modelling
4
Propagation delay :
through the gate, and the time taken for the output to actually
change state, according to input.
Gate level modelling delay described below as:-
Rise
Fall Min/Typ/Max values
Turn-off
7/19/2013
Rise delay
5
7/19/2013
Fall delay
7
7/19/2013
buf #(0,2) (out,in);
8
7/19/2013
Turn-off delay
9
The turn-off delay is associated with a gate output transition to the high
impedance value(z) from another value(0,1,x).
Rise Delay 0,x,z -> 1
Ex:
And #( 2:3:4, 3:4:5, 4:5:6) a ( out, i1, i2 );
7/19/2013
#'num'
11
7/19/2013
#'num'
12
And
7/19/2013
Dataflow Modelling
14
7/19/2013
Regular Assignment Delay
16
// same as
wire out;
assign #10 out = in1 & in2;
7/19/2013
Inertial delay
21
7/19/2013
Transport delay
22
7/19/2013
DELAYS IN BEHAVIOURAL MODELLING
23
7/19/2013
REGULAR DELAY CONTROL
24
7/19/2013
INTRA ASSIGNMENT DELAY
25
7/19/2013
26 7/19/2013
ZERO DELAY
28
7/19/2013
SEQENTIAL BLOCKS
29
7/19/2013
30 7/19/2013
PARALLEL BLOCKS
31
7/19/2013
32 7/19/2013
Setup and Holdtime
33
7/19/2013
Thank you
34
?
7/19/2013