DEPARTMENT OF ELECTRICAL ENGINEERING

HSIU-PING INSTITUTE OF TECHNOLOGY

8051

AD96001
AD96028
AD96031
AD96038


1-1 1
1-2 1

2-1 2
2-2 3
2-3 4
2-4 8
8051
3-1 8051 9
3-2 8051 11
3-3 8051 15
3-4 8051 16
3-5 17

4-1 20
4-2 21
4-3 25
4-4 30
4-5 31
32

33

 2.1 4

2.2 4

2.3 5

2.4 5

2.5 6

2.6 6

2.7 7

2.8 8

2.9 8

3.1 8051 11

3.2 MCS-51 16

3.3 17

4.1 22

4.2 22

4.3 23

4.4 24

4.5 8051 30

4.6 31
 4.7 31

4.1 20

4.2 21

1-1

PDA

PC 8051

8051 IC

()

8051

1 -4

1-2
8051 ARM9

2-1
(Stepping motor)

CNC

1.

2.

3.

4.

5.

6.
7.

2-2

==360/

= 360 / (X )

50 200

50
 2.1

2-3
N

SA-AB-BC

2.2

2.2

S1AN

SAS1

S2ABS
90

2.3

2.3

1.

 2.4

2.

2.5
 2.6

3.

1/2

2.7
 2.8

2-4

IC

FT57543AFT5754

2.9
 8051

3-1 8051

8051 8 MCS-51

1981 MCS-51

IC ATMELWinbond

8051

8051

() ,

8051 8051 40 4 8

I/O PORT3 I/O

VCC 5V

VSS

PORT0 I/O

(D07)(A07)

PORT1 I/O
PORT2 I/O

(A815)

RST 2

ALE/PROG

1/6

PROM

PESN

2 ROM ROM /OE

EA/VPP

EPROM 21V

XTAL1, XTAL2=/12
3-2 8051

3.1 8051

8051

8 8051 1/0 Pl 1 (P1.0)

LSB 8 (P1.7) MSB 8052(8032

8752)Pl.0 Timer2
PI.O~P1.7 1~8

P1.1 T2EX

Pl 4 LS TTL

8051 (RESET)

High(+5V)8051 8051
RESET 9
0000H

(SFR)
 8 8051 I/0 P3 10
(P3.0)
LSB 17 (P3.7)MSBP3 I/O
/
8051
I/O P3.0

P3.1 RxD TxD 8051

UART UART TxD

UART
INTO INTl 8051
T0 Timer0 T1 Timer

WR,RD 8051
P3.0~P3.7 10~17

(RAM)
P3 I/O 8051

P3 I/O ?

8051

UART I0 RxD 11

TxD

1( TxDRxDRDWR...
)P3 I/O 4
LS
TTL
8051

XTAL2~XTALl 18~19
l2MHz
(Crystal)
 l2MHz

8051

lMHzh~12MHz



(Clock) 8051

8051 18
(XTAL2)
19 (XTALl)
NMOS
8051( 8051AH) CMO5 8051
(80C5180C31 ) 19
(XTALl) 18


8051 40
Vee~Vss 40~20 20
5V l0%
8 8052 I/O P2,P2.O
LSB,P2.7
(P2.O--P2.7) MSB I/O

8051
P2.O~P2.7 21~28 P2
8051 (
A8-a15>
P2 I/O P2 I/O

4 LS TTL
8 8051 I/O P0.0 P0.0
PO.O~P0.7 39~32

 LSBP0.7 MSB PO I/0

P0 Open Drain
I/O
(P1,P2P3) pull high P0
I/O
8051

PO (AO~A7)

(DO~D7) 8

PO AO-A7

P2 A8--A15 16

8051 64K
8051

(PSEN) EP
ROM OE 8051 PSEN RD

EPROM ( ) RAM (
PSEN 29
)
8051


64K
8051 128K
""(Address
Latch
Enable ALE),8051
ALE 30
8 PO
(AO~A7)

 EA=O 8051

8051 4K

EA 31

EA +5V 8031( 8032)

EA

3-3 8051

8051 5

1. - ADD()

2. - ANL( AND )

3. - MOV()

4. Boolean - CPL(0 1 )

5. - RET() JNZ(A 0 ) DJNZ(,

0 )
3-4 8051

8051 Intel MCS-51

3.2 MCS-51

8051

1. 8

2.

3. 128 RAM 4K ROM

4. 4 8 I/O

5. 2 16 /

6. UART

7. 5
 8.

64

3-5

3.3

CPU(Center Processing Unit)

1. (Arithmetic Logic Unit ALU)



()(ANDORNOT )

2. (Control Unit CU)

(Decode)(Execute)

3. (Input Unit IU)

CPU

4. (Output Unit OU)

 CPU

5. (Memory Unit MU)

(Main Memory)

(Auxiliary Memory)

(Read Only Memory ROM)

(Random Access Memory RAM)ROM

RAM

RAM


4-1
8051

( 4.1) :

1 X

2 Y

3 Z

4.1

( 4.1)

XYZ 1

3 Y Y

3 4

X X

:1. 2. 3.
4-2
:

1 1

2 1

3 1

4 3

5 1

6 4

7 2

4.2


4.1

15 15 50

14 14 12 (50/4=12.5)

4.2

4.2


(4.3)

4.3
(4.4)

4.4
4-3
-------------
--------------------------
-------------
START: MOV A,P1

MOV R0,A

MOV A,P2

MOV R1,A

ANL A,#0FH

CJNE A,#0EH,NEXT1 ;

NEXT1: CJNE A,#0DH,NEXT2 ;

NEXT2: CJNE A,#0BH,NEXT3 ;

NEXT3: CJNE A,#07H,NEXT4 ;

NEXT4: AJMP START

------------------------------------------------------------

FLOOR1: MOV A,R1 ;

CJNE A,#0EH,F12

AJMP START

F12: CJNE A,#0DH,F13 ;

ANL A,#0FH

CPL A

ANL A,#0FH
 CALL STEP_F

AJMP START

F13: CJNE A,#0BH,F14 ;

ANL A,#0FH

CPL A

ANL A,#0FH

CALL STEP_F

AJMP START

F14: ANL A,#0FH ;

CPL A

ANL A,#0FH

CALL STEP_F

AJMP START

------------------------------------------------------------

FLOOR2: MOV A,R1 ;

CJNE A, #0EH,F22

ORL A, #0F0H

CPL A

CALL STEP_B

AJMP START

F22: CJNE A,#0DH,F23

 AJMP START

F23: CJNE A,#0BH,F24 ;

ORL A,#0F0H

CPL A

CLR C

SUBB A,#03H

CALL STEP_F

AJMP START

F24: MOV A,#02H ;

CALL STEP_F

AJMP START

------------------------------------------------------------

FLOOR3: MOV A,R1 ;

CJNE A,#0EH,F32

MOV A,#02H

CALL STEP_B

AJMP START

F32: CJNE A,#0DH,F33 ;

MOV A,#01H

CALL STEP_B

AJMP START
F33: CJNE A,#0BH,F34

AJMP START

F34: MOV A,#01H ;

CALL STEP_F

AJMP START

------------------------------------------------------------

FLOOR4: MOV A,R1 ;

CJNE A,#0EH,F42

MOV A,#03H

CALL STEP_B

AJMP START

F42: CJNE A,#0DH,F43 ;

MOV A,#02

CALL STEP_B

AJMP START

F43: CJNE A,#0BH,F44 ;

MOV A,#01H

CALL STEP_B

AJMP START

F44: AJMP 22START

 ------------------------------------------------------------

STEP_F: MOV R0,A ;

MOV A,#33H

FL1: MOV R1,#200

FL2: MOV P3,A

CALL DELAY

RL A

DJNZ R1,FL2

DJNZ R0,FL1

RET

STEP_B: MOV R0,A ;

MOV A,#33H

BL1: MOV R1,#200

BL2: MOV P3,A

CALL DELAY

RR A

DJNZ R1,BL2

DJNZ R0,BL1

RET

DELAY: MOV R3,#10 ;

S1: MOV R4,#100

S2: MOV R5,#200

S3: NOP

NOP

NOP

DJNZ R5,S3

DJNZ R4,S2

DJNZ R3,S1

RET

END

4-4 8051

4.5 8051
4-5

4.6

4-6

4.7

8051 8051

8051

AD96038 (8051 )

AD96001 ( )

AD96028 ( )

AD96031 ( )

1.8051 - C

1. http://www.ee.thit.edu.tw/~microlab/8051/pin.htm

2. http://www.twivs.tnc.edu.tw/teachhome/51/instr.htm

3. http://elearning.stut.edu.tw/mechelec/ch3.htm