xiv Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Digital Calibration of Analog Circuits and Systems Up/down current mirror principle Smooth transition during up/down step Up/down current mirror schematic Up/down current mirror micrograph 2-pass simulation algorithm. Single-ended compensation component in the schematic editor Differential compensation component in the schematic editor Single-ended compensation component netlist for the first pass Model of the analog feedback loop of the first pass Differential compensation component netlist for the first pass Single-ended compensation component netlist for the second pass Final value range of the successive approximations algorithm Differential compensation component netlist for the second pass Modified 2-pass simulation algorithm PSpice diode model Programmable current source Untrimmed offset of a typical Miller amplifier Miller amplifier offset with single-ended 8-bits trimming SOIL 1T DRAM cell Read current dispersion of the 1T DRAM cell Retention characteristics of the 1T DRAM cell Reference current window as a function of time Sense amplifier for SO1 1T DRAM Sense amplifier model Automatic reference adjustment algorithm Optimized automatic reference adjustment algorithm Write/read cycles on 3 adjacent memory cells Hall effect 118 119 122 124 125 126 127 128 128 130 131 132 133 134 135 136 137 138 139 140 141 141 142 143 145 147 148 152