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PIC16 (L) F1454/5/9 Data Sheet: 14/20-Pin Flash, 8-Bit USB Microcontrollers With XLP Technology
PIC16 (L) F1454/5/9 Data Sheet: 14/20-Pin Flash, 8-Bit USB Microcontrollers With XLP Technology
Data Sheet
14/20-Pin Flash, 8-Bit USB Microcontrollers
with XLP Technology
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
ISBN: 9781620763476
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
CERTIFIED BY DNV headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
== ISO/TS 16949 == are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
MSSP (I2C/SPI)
Data Sheet Index
Clock Reference
10-bit ADC (ch)
Flash (words)
Comparators
Data SRAM
(8/16-bit)
EUSART
Debug(1)
(bytes)
Timers
I/Os(2)
PWM
CWG
DAC
USB
XLP
Device
Note: For other small form-factor package availability and marking information, please visit
www.microchip.com/packaging or contact your local sales office.
PIC16(L)F1454
PIC16(L)F1455
RA4 3 12 RA1/D-/ICSPCLK(1)
MCLR/VPP/RA3 4 11 VUSB3V3
RC5 5 10 RC0/ICSPDAT
RC4 6 9 RC1/ICSPCLK
RC3 7 8 RC2
QFN (4x4)
VDD
Vss
NC
NC
16 15 14 13
RA5 1 12 RA0/D+/ICSPDAT(1)
RA4 2 PIC16(L)F1454 11 RA1/D-/ICSPCLK(1)
MCLR/VPP/RA3 3 PIC16(L)F1455
10 VUSB3V3
RC5 4 9 RC0/ICSPDAT
5 6 7 8
RC4
RC3
ICSPCLK/RC1
RC2
VDD 1 20 VSS
RA5 2 19 RA0/D+/ICSPDAT(1)
RA4 3 18 RA1/D-/ICSPCLK(1)
MCLR/VPP/RA3 4 17 VUSB3V3
PIC16(L)F1459
RC5 5 16 RC0/ICSPDAT
RC4 6 15 RC1/ICSPCLK
RC3 7 14 RC2
RC6 8 13 RB4
RC7 9 12 RB5
RB7 10 11 RB6
QFN (4x4)
RA0/D+/ICSPDAT(1)
RA4
RA5
VDD
Vss
20 19 18 17 16
MCLR/VPP/RA3 1 15 RA1/D-/ICSPCLK(1)
RC5 2 14 VUSB3V3
RC4 3 PIC16(L)F1459 13 RC0/ICSPDAT
RC3 4 12 RC1/ICSPCLK
RC6 5 11 RC2
6 7 8 9 10
RB5
RC7
RB7
RB6
RB4
14-Pin PDIP/SOIC/TSSOP
Comparator
16-Pin QFN
Reference
EUSART
Interrupt
MSSP
Timer
Basic
PWM
CWG
ADC
USB
I/O
14-Pin PDIP/SOIC/TSSOP
Comparator
16-Pin QFN
Reference
EUSART
Interrupt
MSSP
Timer
Basic
PWM
CWG
ADC
USB
I/O
20-Pin PDIP/SOIC/SSOP
Comparator
20-Pin QFN
Reference
EUSART
Interrupt
MSSP
Timer
Basic
PWM
CWG
ADC
USB
I/O
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
PIC16LF1454
PIC16LF1455
PIC16LF1459
PIC16F1459
PIC16F1454
PIC16F1455
Peripheral
Program
Flash Memory
RAM
OSC2/CLKOUT Timing
Generation PORTA
OSC1/CLKIN CPU
INTRC
Oscillator PORTB(2)
(Figure 2-1)
MCLR
PORTC
Temp. ADC
EUSART FVR(1) PWM1 PWM2 MSSP1 DAC(1)
Indicator(1) 10-Bit(1)
15
Configuration 15 8
Data Bus
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Instruction Timer
Decodeand
Decode & ALU
Control Power-on
Reset
OSC1/CLKIN 8
Watchdog
Timing Timer
OSC2/CLKOUT Generation W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS
Rollover to Page 3
7FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
CPU Banked Address CPU Linear Address USB Banked Address USB Linear Address
020 - 06F 2000 - 204F 020 - 06F 2000 - 204F
0A0 - 0EF 2050 - 209F 0A0 - 0EF 2050 - 209F
120 - 16F 20A0 - 20EF 120 - 16F 20A0 - 20EF
1A0 - 1EF 20F0 - 213F 1A0 - 1EF 20F0 - 213F
220 - 26F 2140 - 218F 220 - 26F 2140 - 218F
2A0 - 2EF 2190 - 21DF 2A0 - 2EF 2190 - 21DF
320 - 32F 21E0 - 21EF 320 - 32F 21E0 - 21EF
370 - 37F (1) 370 - 37F (1)
Note 1: Accessible from banked memory only.
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h (1)
OR
6Fh
70h
Common RAM
(16 bytes)
7Fh
PIC16(L)F1454/5/9
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch 20Ch WPUA 28Ch 30Ch 38Ch
00Dh 08Dh 10Dh 18Dh 20Dh 28Dh 30Dh 38Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh 20Eh 28Eh 30Eh 38Eh
00Fh 08Fh 10Fh 18Fh 20Fh 28Fh 30Fh 38Fh
010h 090h 110h 190h 210h 290h 310h 390h
011h PIR1 091h PIE1 111h 191h PMADRL 211h SSP1BUF 291h 311h 391h IOCAP
012h PIR2 092h PIE2 112h 192h PMADRH 212h SSP1ADD 292h 312h 392h IOCAN
013h 093h 113h 193h PMDATL 213h SSP1MSK 293h 313h 393h IOCAF
014h 094h 114h 194h PMDATH 214h SSP1STAT 294h 314h 394h
015h TMR0 095h OPTION_REG 115h 195h PMCON1 215h SSP1CON1 295h 315h 395h
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 316h 396h
017h TMR1H 097h WDTCON 117h 197h VREGCON 217h SSP1CON3 297h 317h 397h
018h T1CON 098h OSCTUNE 118h 198h 218h 298h 318h 398h
019h T1GCON 099h OSCCON 119h 199h RCREG 219h 299h 319h 399h
01Ah TMR2 09Ah OSCSTAT 11Ah 19Ah TXREG 21Ah 29Ah 31Ah 39Ah CLKRCON
Preliminary
01Bh PR2 09Bh 11Bh 19Bh SPBRG 21Bh 29Bh 31Bh 39Bh CRCON
01Ch T2CON 09Ch 11Ch 19Ch SPBRGH 21Ch 29Ch 31Ch 39Ch
01Dh 09Dh 11Dh APFCON 19Dh RCSTA 21Dh 29Dh 31Dh 39Dh
01Eh 09Eh 11Eh 19Eh TXSTA 21Eh 29Eh 31Eh 39Eh
01Fh 09Fh 11Fh 19Fh BAUDCON 21Fh 29Fh 31Fh 39Fh
020h 0A0h 120h 1A0h 220h 2A0h 320h Dual-Port 3A0h
General
Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Purpose
General
General General General General General General Register
Purpose
Purpose Purpose Purpose Purpose Purpose Purpose 32Fh 16Bytes
Register
Register Register Register Register Register Register 330h General 80 Bytes
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Purpose
Register
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 64 Bytes 3EFh
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Dual-Port
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
Common RAM
70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh)
2012 Microchip Technology Inc.
01Bh PR2 09Bh ADRESL 11Bh 19Bh SPBRG 21Bh 29Bh 31Bh 39Bh CRCON
01Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch 29Ch 31Ch 39Ch
01Dh 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh 29Dh 31Dh 39Dh
01Eh 09Eh ADCON1 11Eh 19Eh TXSTA 21Eh 29Eh 31Eh 39Eh
01Fh 09Fh ADCON2 11Fh 19Fh BAUDCON 21Fh 29Fh 31Fh 39Fh
020h 0A0h 120h 1A0h 220h 2A0h 320h Dual-Port 3A0h
General
Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Purpose
General
General General General General General General Register
Purpose
PIC16(L)F1454/5/9
Purpose Purpose Purpose Purpose Purpose Purpose 32Fh 16Bytes
Register
Register Register Register Register Register Register 330h General 80 Bytes
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Purpose
Register
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 64 Bytes 3EFh
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Dual-Port
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
Common RAM
70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
PIC16(L)F1454/5/9
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 30Ch 38Ch
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 30Dh 38Dh
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh 28Eh 30Eh 38Eh
00Fh 08Fh 10Fh 18Fh 20Fh 28Fh 30Fh 38Fh
010h 090h 110h 190h 210h 290h 310h 390h
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h SSP1BUF 291h 311h 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h SSP1ADD 292h 312h 392h IOCAN
013h 093h 113h CM2CON0 193h PMDATL 213h SSP1MSK 293h 313h 393h IOCAF
014h 094h 114h CM2CON1 194h PMDATH 214h SSP1STAT 294h 314h 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 315h 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 316h 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h 317h 397h
018h T1CON 098h OSCTUNE 118h DACCON0 198h 218h 298h 318h 398h
019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h 299h 319h 399h
01Ah TMR2 09Ah OSCSTAT 11Ah 19Ah TXREG 21Ah 29Ah 31Ah 39Ah CLKRCON
Preliminary
01Bh PR2 09Bh ADRESL 11Bh 19Bh SPBRG 21Bh 29Bh 31Bh 39Bh CRCON
01Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch 29Ch 31Ch 39Ch
01Dh 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh 29Dh 31Dh 39Dh
01Eh 09Eh ADCON1 11Eh 19Eh TXSTA 21Eh 29Eh 31Eh 39Eh
01Fh 09Fh ADCON2 11Fh 19Fh BAUDCON 21Fh 29Fh 31Fh 39Fh
020h 0A0h 120h 1A0h 220h 2A0h 320h Dual-Port 3A0h
General
Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Dual-Port Purpose
General
General General General General General General Register
32Fh 16Bytes Purpose
Purpose Purpose Purpose Purpose Purpose Purpose
Register
Register Register Register Register Register Register 330h General
80 Bytes
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes Purpose
Register
64 Bytes 3EFh
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Dual-Port
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
Common RAM
70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh)
2012 Microchip Technology Inc.
PIC16(L)F1454/5/9
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh) 70h 7Fh)
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
PIC16(L)F1454/5/9
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h 480h 500h 580h 600h 680h 700h 780h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch 48Ch 50Ch 58Ch 60Ch 68Ch 70Ch 78Ch
40Dh 48Dh 50Dh 58Dh 60Dh 68Dh 70Dh 78Dh
40Eh 48Eh 50Eh 58Eh 60Eh 68Eh 70Eh 78Eh
40Fh 48Fh 50Fh 58Fh 60Fh 68Fh 70Fh 78Fh
410h 490h 510h 590h 610h 690h 710h 790h
411h 491h 511h 591h 611h PWM1DCL 691h CWG1DBR 711h 791h
412h 492h 512h 592h 612h PWM1DCH 692h CWG1DBF 712h 792h
413h 493h 513h 593h 613h PWM1CON 693h CWG1CON0 713h 793h
414h 494h 514h 594h 614h PWM2DCL 694h CWG1CON1 714h 794h
415h 495h 515h 595h 615h PWM2DCH 695h CWG1CON2 715h 795h
416h 496h 516h 596h 616h PWM2CON 696h 716h 796h
417h 497h 517h 597h 617h 697h 717h 797h
418h 498h 518h 598h 618h 698h 718h 798h
419h 499h 519h 599h 619h 699h 719h 799h
41Ah 49Ah 51Ah 59Ah 61Ah 69Ah 71Ah 79Ah
41Bh 49Bh 51Bh 59Bh 61Bh 69Bh 71Bh 79Bh
41Ch 49Ch 51Ch 59Ch 61Ch 69Ch 71Ch 79Ch
Preliminary
PIC16(L)F1454/5/9
Read as 0 Read as 0 Read as 0 Read as 0 Read as 0 Read as 0 Read as 0
Bank 31
F8Ch
Unimplemented
Read as 0
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Bank 0-31
x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory
INDF0 xxxx xxxx uuuu uuuu
x80h (not a physical register)
x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory
INDF1 xxxx xxxx uuuu uuuu
x81h (not a physical register)
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS TO PD Z DC C ---1 1000 ---q quuu
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR BSR<4:0> ---0 0000 ---0 0000
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.
Shaded locations are unimplemented, read as 0.
Bank 0
00Ch PORTA RA5 RA4 RA3 RA1 RA0 --xx x-xx --xx x-xx
00Dh PORTB(1) RB7 RB6 RB5 RB4 xxxx ---- xxxx ----
00Eh PORTC RC7(1) RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx
00Fh Unimplemented
010h Unimplemented
011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 0000 0-00 0000 0-00
012h PIR2 OSFIF C2IF C1IF BCL1IF USBIF ACTIF 000- 000- 000- 000-
013h Unimplemented
014h Unimplemented
015h TMR0 Holding Register for the 8-bit Timer0 Count xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer2 Period Register 1111 1111 1111 1111
01Ch T2CON T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh Unimplemented
01Eh Unimplemented
01Fh Unimplemented
Bank 1
08Ch TRISA TRISA5 TRISA4 (2) (2) (2) --11 ---- --11 ----
(1)
08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----
08Eh TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
08Fh Unimplemented
090h Unimplemented
091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 0000 0-00 0000 0-00
092h PIE2 OSFIE C2IE C1IE BCL1IE USBIE ACTIE 000- 000- 000- 000-
093h Unimplemented
094h Unimplemented
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h OSCTUNE TUN<6:0> -000 0000 -uuu uuuu
099h OSCCON SPLLEN SPLLMULT IRCF<3:0> SCS<1:0> 0011 1100 0011 1100
09Ah OSCSTAT SOSCR PLLRDY OSTS HFIOFR LFIOFR HFIOFS 00q0 --00 qqqq --qq
09Bh ADRESL(2) A/D Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH(2) A/D Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0(2) CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1(2) ADFM ADCS<2:0> ADPREF<1:0> 0000 --00 0000 --00
09Fh ADCON2(2) TRIGSEL<2:0> -000 ---- -000 ----
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
Bank 2
10Ch LATA LATA5 LATA4 --xx ---- --uu ----
10Dh LATB(1) LATB7 LATB6 LATB5 LATB4 xxxx ---- uuuu ----
10Eh LATC LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu
10Fh Unimplemented
110h Unimplemented
111h CM1CON0(2) C1ON C1OUT C1OE C1POL C1SP C1HYS C1SYNC 0000 -100 0000 -100
112h CM1CON1(2) C1INTP C1INTN C1PCH<1:0> C1NCH<2:0> 0000 -000 0000 -000
113h CM2CON0(2) C2ON C2OUT C2OE C2POL C2SP C2HYS C2SYNC 0000 -100 0000 -100
114h CM2CON1(2) C2INTP C2INTN C2PCH<1:0> C2NCH<2:0> 0000 -000 0000 -000
115h CMOUT(2) MC2OUT MC1OUT ---- --00 ---- --00
116h BORCON SBOREN BORFS BORRDY 10-- ---q uu-- ---u
117h FVRCON(2) FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000
118h DACCON0(2) DACEN DACOE1 DACOE2 DACPSS<1:0> 0-00 00-- 0-00 00--
119h DACCON1(2) DACR<4:0> ---0 0000 ---0 0000
11Ah
to Unimplemented
11Ch
11Dh APFCON CLKRSEL SDOSEL(1) SSSEL T1GSEL P2SEL(1) 000- --00 000- --00
11Eh Unimplemented
11Fh Unimplemented
Bank 3
18Ch ANSELA(2) ANSA4 ---1 ---- ---1 ----
18Dh ANSELB(1) ANSB5 ANSB4 --11 ---- --11 ----
18Eh ANSELC(2) ANSC7(1) ANSC6(1) ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111
18Fh Unimplemented
190h Unimplemented
191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH (2) Flash Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 (2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000
197h VREGCON(1) VREGPM Reserved ---- --01 ---- --01
198h Unimplemented
199h RCREG USART Receive Data Register 0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 01-0 0-00
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
Bank 4
20Ch WPUA WPUA5 WPUA4 WPUA3 --11 1--- --11 1---
20Dh WPUB(1) WPUB7 WPUB6 WPUB5 WPUB4 1111 ---- 1111 ----
20Eh
to Unimplemented
210h
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD ADD<7:0> 0000 0000 0000 0000
213h SSP1MSK MSK<7:0> 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
218h
to Unimplemented
21Fh
Bank 5
28Ch
to Unimplemented
29Fh
Bank 6
30Ch
to Unimplemented
31Fh
Bank 7
38Ch
to Unimplemented
390h
391h IOCAP IOCAP5 IOCAP4 IOCAP3 IOCAP1 IOCAP0 --00 0-00 --00 0-00
392h IOCAN IOCAN5 IOCAN4 IOCAN3 IOCAN1 IOCAN0 --00 0-00 --00 0-00
393h IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF1 IOCAF0 --00 0-00 --00 0-00
394h IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 0000 ---- 0000 ----
395h IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 0000 ---- 0000 ----
396h IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 0000 ---- 0000 ----
397h
to Unimplemented
399h
39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000
39Bh ACTCON ACTEN ACTUD ACTSRC ACTLOCK ACTORS 00-0 0-0- 00-0 0-0-
39Ch
to Unimplemented
39Fh
Bank 8
40Ch
to Unimplemented
41Fh
Bank 9
48Ch
to Unimplemented
49Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
Bank 10
50Ch
to Unimplemented
51Fh
Bank 11
58Ch
to Unimplemented
59Fh
Bank 12
60Ch
to Unimplemented
610h
611h PWM1DCL PWM1DCL<7:6> 00-- ---- 00-- ----
612h PWM1DCH PWM1DCH<7:0> xxxx xxxx uuuu uuuu
613h PWM1CON0 PWM1EN PWM1OE PWM1OUT PWM1POL 0000 ---- 0000 ----
614h PWM2DCL PWM2DCL<7:6> 00-- ---- 00-- ----
615h PWM2DCH PWM2DCH<7:0> xxxx xxxx uuuu uuuu
616h PWM2CON0 PWM2EN PWM2OE PWM2OUT PWM2POL 0000 ---- 0000 ----
617h
to Unimplemented
61Fh
Bank 13
68Ch
to Unimplemented
690h
691h CWG1DBR(2) CWG1DBR<5:0> --00 0000 --00 0000
692h CWG1DBF(2) CWG1DBF<5:0> --xx xxxx --xx xxxx
693h CWG1CON0(2) G1EN G1OEB G1OEA G1POLB G1POLA G1CS0 0000 0--0 0000 0--0
694h CWG1CON1(2) G1ASDLB<1:0> G1ASDLA<1:0> G1IS<1:0> 0000 --00 0000 --00
695h CWG1CON2(2) G1ASE G1ARSEN G1ASDC2 G1ASDC1 G1ASDSFLT 00-- 0001 00-- 000-
696h
to Unimplemented
69Fh
Banks 14-28
x0Ch/ Unimplemented
x8Ch
x1Fh/
x9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
Bank 29
E8Ch Unimplemented
E8Dh Unimplemented
E8Eh UCON PPBRST SE0 PKTDIS USBEN RESUME SUSPND -0x0 000- -0u0 000-
E90h UIR SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 -000 0000
E91h UCFG UTEYE Reserved UPUEN Reserved FSEN PPB<1:0> 00-0 -000 00-0 -000
E92h UIE SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 -000 0000
E93h UEIR BTSEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 -000 0--0 -000
E94h UFRMH FRM10 FRM9 FRM8 ---- -xxx ---- -uuu
E95h UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx uuuu uuuu
E96h UADDR ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 -000 0000
E97h UEIE BTSEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 0--0 0000
E98h UEP7 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E99h UEP6 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Ah UEP5 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Bh UEP4 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Ch UEP3 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Dh UEP2 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Eh UEP1 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
E9Fh UEP0 EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 ---0 0000
Bank 30
F0Ch Unimplemented
F1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
Bank 31
F8Ch Unimplemented
FE3h
FE4h STATUS_ Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
SHAD
FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu
SHAD
FE6h BSR_ Bank Select Register Shadow ---x xxxx ---u uuuu
SHAD
FE7h PCLATH_ Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu
SHAD
FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu
SHAD
FECh Unimplemented
FEDh STKPTR Current Stack Pointer ---1 1111 ---1 1111
FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH Top-of-Stack High byte -xxx xxxx -uuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
3: Unimplemented, read as 1.
6 7 0 8
3.4.4 BRANCHING
PCLATH W
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
14 PCH PCL 0
PC BRW page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
15 the next instruction in both cases. When using either
PC + W branching instruction, a PCL memory boundary may be
crossed.
14 PCH PCL 0
If using BRW, load the W register with the desired
PC BRA
unsigned address and execute BRW. The entire PC will
15 be loaded with the address PC + 1 + W.
PC + OPCODE <8:0>
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
TOSH:TOSL 0x06 Return Address STKPTR = 0x06
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
0x7F
Bank 0 Bank 1 Bank 2 Bank 31
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as 1
0 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Once enabled (CP = 0), code-protect can only be disabled by bulk erasing the device.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as 1
0 = Bit is cleared 1 = Bit is set -n = Value when blank or after Bulk Erase
Note 1: The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
2: See Vbor parameter for specific trip point voltages.
3: The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.
4.5 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.4 User ID, Device ID and Configuration
Word Access for more information on accessing these
memory locations. For more information on checksum
calculation, see the PIC16(L)F1454/5/9 Memory
Programming Specification (DS41620).
R R R R R R R R
DEV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
1 = Bit is set 0 = Bit is cleared
R R R R R R R R
REV<7:0>
bit 7 bit 0
Legend:
R = Readable bit
1 = Bit is set 0 = Bit is cleared
SPLLMULT SPLLEN
FOSC<2:0> PLLMULT PLLEN
3
CLKIN/ OSC1/ INTOSC
SOSCI/ T1CKI (16 or 8 MHz) 3x/4x PLL CPUDIV<1:0>
Primary
Oscillator Primary Clock CPU FOSC
1
(OSC) Divider to
0 CPU and
CLKOUT / OSC2 Peripherals
SOSCO/ T1G SOSC_clk Secondary Clock FSEN
Secondary
Oscillator 48 MHz
(SOSC) INTOSC 1 USB
IRCF<3:0> USB 6 MHz
4 0 Clock
Active Clock
Divider Source
Tuning 16 MHz
8 MHz
USBLSCLK
4 MHz
16 MHz 2 MHz
Clock Sleep
Internal OSC 1 MHz
Postscaler
HFINTOSC Control
500 kHz
Start-Up
OSC 250 kHz
125 kHz
Start-up 62.5 kHz 2
Control Logic 31.25 kHz SCS<1:0>
3
31 kHz FOSC<2:0>
EC mode has three power modes to select from through Figure 5-3 and Figure 5-4 show typical circuits for
Configuration Words: quartz crystal and ceramic resonators, respectively.
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
OSC2/CLKOUT
C2 RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts 1024
expected for the application. oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Applications Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
AN826, Crystal Oscillator Basics and increment and program execution is suspended unless
Crystal Selection for rfPIC and PIC either FSCM or Two-Speed Start-Up are enabled. In this
Devices (DS00826) case, code will continue to execute at the selected
AN849, Basic PIC Oscillator Design INTOSC frequency while the OST is counting . The OST
(DS00849) ensures that the oscillator circuit, using a quartz crystal
AN943, Practical PIC Oscillator resonator or ceramic resonator, has started and is
Analysis and Design (DS00943) providing a stable system clock to the oscillator module.
AN949, Making Your Oscillator Work In order to minimize latency between external oscillator
(DS00949) start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.6
Two-Speed Clock Start-up Mode).
PIC MCU
SOSCI
C1 To Internal
Logic
32.768 kHz
Quartz
Crystal
C2 SOSCO
HFINTOSC
Start-up Time 2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
HFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running
HFINTOSC
IRCF <3:0> =0 0
System Clock
The USB module is designed to operate in two different Table 5-1 shows the recommended Clock mode for
modes: full-speed operation.
Low Speed
Full Speed
To achieve the timing requirements imposed by the
USB specifications, the internal oscillator or the primary
external oscillator are required for the USB module.
The FOSC bits of the Configuration Words must be set
to INTOSC, ECH or HS mode with a clock frequency of
6, 12, or 16 MHz.
Default system oscillator determined by FOSC The secondary oscillator is enabled using the
bits in Configuration Words T1OSCEN control bit in the T1CON register. See
Section 20.0 Timer1 Module with Gate Control for
Secondary oscillator 32 kHz crystal
more information about the Timer1 peripheral.
Internal Oscillator Block (INTOSC)
5.5.4 SECONDARY OSCILLATOR READY
5.5.1 SYSTEM CLOCK SELECT (SCS)
(SOSCR) BIT
BITS
The user must ensure that the secondary oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Secondary Oscillator Ready (SOSCR) bit
the CPU and peripherals.
of the OSCSTAT register indicates whether the
When the SCS bits of the OSCCON register = 00, secondary oscillator is ready to be used. After the
the system clock source is determined by value of SOSCR bit is set, the SCS bits can be configured to
the FOSC<2:0> bits in the Configuration Words. select the secondary oscillator.
When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-3.
INTOSC
TOST
OSC2
Program Counter PC - N PC PC + 1
System Clock
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
ACTSRC ACTEN
FSUSB_clk 1 Enable
ACT_clk 16 MHz
Internal OSC
SOSC_clk 0 Active
Clock
Tuning ACT data sfr data
7 7
Write
OSCTUNE<6:0> OSCTUNE
ACTUD
ACTEN
ACTEN
5.8.6 INTERRUPTS
The ACT will set the ACT Interrupt Flag, (ACTIF) when
either of the ACT Status bits (ACTLOCK or ACTORS)
change state, regardless if the interrupt is enabled,
(ACTIE = 1). The ACTIF and ACTIE bits are in the PIRx
and PIEx registers, respectively. When ACTIE = 1, an
interrupt will be generated whenever the ACT Status
bits change.
The ACTIF bit must be cleared in software, regardless
of the interrupt enable setting.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Conditional
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When active clock tuning is enabled (ACTSEL = 1) the oscillator is tuned automatically, the user cannot
write to OSCTUNE.
2: Oscillator is tuned monotonically.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Stack
Pointer
MCLRE
MCLR
Sleep
WDT
Time-out Device
Reset
Power-on
Reset
VDD
Brown-out PWRT
R
Reset Done
LPBOR
Reset PWRTE
LFINTOSC
BOR
Active(1)
6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
When the BOREN bits of Configuration Words are pro-
grammed to 11, the BOR is always on. The device
6.2.3 BOR CONTROLLED BY SOFTWARE
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold. When the BOREN bits of Configuration Words are
programmed to 01, the BOR is controlled by the
BOR protection is active during Sleep. The BOR does
SBOREN bit of the BORCON register. The device
not delay wake-up from Sleep.
start-up is not delayed by the BOR ready condition or
the VDD level.
6.2.2 BOR IS OFF IN SLEEP
BOR protection begins as soon as the BOR circuit is
When the BOREN bits of Configuration Words are pro-
ready. The status of the BOR circuit is reflected in the
grammed to 10, the BOR is on, except in Sleep. The
BORRDY bit of the BORCON register.
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep.
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration
Words = 0 will result in FOSC/4. See Section 7.3 Conflicts with the CLKR Pin for details.
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF Interrupt
(TMR1IF) PIR1<0> IOCIE to CPU
PEIE
PIRn<7>
PIEn<7> GIE
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Interrupt
GIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) Inst (0004h) Inst (0005h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register
have been cleared by software.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
WDTE<1:0> = 01
SWDTEN
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
End
Read Operation
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here
RD bit
PMDATH
PMDATL
Register
Unlock Sequence
Figure 11-3
(FIGURE x-x)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
PIC16(L)F1454/5/9
7 6 0 7 5 4 0 7 5 0 7 0
PMADRH PMADRL - - PMDATH PMDATL
- r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0 6 8
14
Program Memory Write Latches
10 5
14 14 14 14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
PMADRL<4:0> 00h 01h 1Eh 1Fh
14 14 14 14
Preliminary
800h 8000h - 8003h 8004h 8005h 8006h 8007h 8008h 8009h - 801Fh
Configuration
USER ID 0 - 3 reserved REVID DEVID reserved
Words
CFGS = 1
Configuration Memory
PIC16(L)F1454/5/9
FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Unlock Sequence
Select
Last word to Yes (Figure11-3
Figure x-x)
Program or Config. Memory
(CFGS) write ?
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Write Operation
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
Erase Operation
(Figure11-4
Figure x.x)
WRITE Operation
use RAM image
(Figure11-5
Figure x.x)
End
Modify Operation
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8005h-8006h Revision ID-Device ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
Start
Verify Operation
Read Operation
(Figure
Figure x.x)
11-2
PMDAT = No
RAM image
?
Yes Fail
Verify Operation
No Last
Word ?
Yes
End
Verify Operation
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Some ports may have one or more of the following Write LATx
Write PORTx
additional registers. These registers are: CK VDD
ANSELx (analog select) Data Register
WPUx (weak pull-up)
Data Bus
In general, when a peripheral is enabled on a port pin,
I/O pin
that pin cannot be used as a general purpose output. Read PORTx
However, the pin can still be read.
To peripherals
VSS
ANSELx
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
EXAMPLE 12-1: INITIALIZING PORTA
PORTB
PORTA
PORTC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: PIC16(L)F1455/9 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
return of actual I/O pin values.
2: PIC16(L)F1459 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-6 ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 5-4 Unimplemented: Read as 0
bit 3-0 ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: PIC16(L)F1459 only.
IOCANx D Q4Q1
Q
CK Edge
Detect
R
RAx
CK Write IOCAFx CK
IOCIE
R
Q2
From all other
IOCAFx individual IOC interrupt
Pin Detectors to CPU core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS - Bit is set in hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS - Bit is set in hardware
ADFVR<1:0>
2
X1
X2 FVR BUFFER1
X4 (To ADC Module)
CDAFVR<1:0> 2
X1
X2 FVR BUFFER2
X4 (To Comparators, DAC)
+
FVREN
_ FVRRDY
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> 150
Legend: Shaded cells are unused by the Fixed Voltage Reference module.
High Range: VOUT = VDD - 4VT TABLE 15-1: RECOMMENDED VDD VS.
RANGE
Low Range: VOUT = VDD - 2VT Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
3.6V 1.8V
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See 15.3 Temperature Output
Section Register 14-1: FVRCON: Fixed Voltage
Reference Control Register for more information. The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
The circuit is enabled by setting the TSEN bit of the the temperature circuit output. Refer to Section 16.0
FVRCON register. When disabled, the circuit draws no Analog-to-Digital Converter (ADC) Module
current. (PIC16(L)F1455/9 only) for detailed information.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the 15.4 ADC Acquisition Time
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range, To ensure accurate temperature measurements, the
but may be less consistent from part to part. This range user must wait at least 200 s after the ADC input
requires a higher bias voltage to operate and thus, a multiplexer is connected to the temperature indicator
higher VDD is needed. output before the conversion is performed. In addition,
the user must wait 200 s between sequential
The low range is selected by clearing the TSRNG bit of
conversions of the temperature indicator output.
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
VDD
ADPREF = 00
VREF+ ADPREF = 10
CHS<4:0>
ADC
ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
(2) (2) (2)
Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s
Fosc/8 001 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
(3)
Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s(3)
(3) (3)
Fosc/64 110 3.2 s 4.0 s 8.0 s 16.0 s 64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 29.0 Electrical Specifications for details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
1
V AP P LI ED 1 -------------------------- = V CHOLD ;[1] VCHOLD charged to within 1/2 lsb
n+1
2 1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
Tc
---------
1
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------- ;combining [1] and [2]
RC
n+1
2 1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 12.5pF 1k + 7k + 10k ln(0.0004885)
= 1.12 s
Therefore:
T A CQ = 5s + 1.12 s + 50C- 25C 0.05 s/C
= 7.37s
Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
VREF-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
VREF- Zero-Scale
Transition Full-Scale
Transition VREF+
V OUT = V SOURCE +
V OUT = V SOURCE
VDD
VSOURCE+
DACR<4:0>
5
VREF+
R
R
DACPSS
R
DACEN
R
32-to-1 MUX
32
Steps DAC
(To Comparator and
ADC Module)
R
R
DACOUT1
R
DACOE1
VSOURCE- DACOUT2
DACOE2
PIC MCU
DAC
R
Module
+
Voltage DACOUTX Buffered DAC Output
Reference
Output
Impedance
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
det
Reserved 0
Set CxIF
CXIN1- 1
MUX Interrupt CxINTN
CXIN2- 2 (2)
det
CXIN3- CXPOL
3
CxVN
-
FVR Buffer2 CXOUT
4 D Q
Cx MCXOUT
+
CxVP
Q1 EN
CXIN+ 0
MUX CxHYS
DAC 1 (2) CxSP
async_CxOUT
To CWG
FVR Buffer2 2
3
CXSYNC
CxON CXOE
TRIS bit
CXOUT
CXPCH<1:0> 0
2
D Q 1
(from Timer1)
T1CLK
SYNCCXOUT To Timer1,
ADC
Note 1: When CxON = 0, the Comparator will produce a 0 at the output
2: When CxON = 0, all multiplexer inputs are disconnected.
CPIN ILEAKAGE(1)
VA VT 0.6V
5 pF
Vss
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
FOSC/4
Data Bus
0
8
T0CKI 1
Sync
1 2 TCY TMR0
0
TMR0SE TMR0CS Set Flag bit TMR0IF
8-bit on Overflow
Prescaler PSA
Overflow to Timer1
PS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
T1GSS<1:0>
T1G 00 T1GSPM
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Sets Flag
TMR2
bit TMR2IF
Output
Prescaler Reset
FOSC/4 TMR2
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS<1:0>
PR2 4
T2OUTPS<3:0>
A 4-bit counter/prescaler on the clock input allows direct Timer2 can be optionally used as the shift clock source
input, divide-by-4 and divide-by-16 prescale options. for the MSSP module operating in SPI mode.
These options are selected by the prescaler control bits, Additional information is provided in Section 22.1
T2CKPS<1:0> of the T2CON register. The value of Master SSP (MSSP) Module Overview.
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the 21.4 Timer2 Operation During Sleep
comparator generates a match signal as the timer
Timer2 cannot be operated while the processor is in
output. This signal also resets the value of TMR2 to 00h
Sleep mode. The contents of the TMR2 and PR2
on the next cycle and drives the output counter/
registers will remain unchanged while the processor is
postscaler (see Section 21.2 Timer2 Interrupt).
in Sleep mode.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
a write to the TMR2 register
a write to the T2CON register
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note: TMR2 is not cleared when T2CON is
written.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Data Bus
Read Write
SSPBUF Reg
SDI
SDO_out
SSPSR Reg
SDO bit 0 Shift
Clock
Edge
Select
SCK_out
SSPM<3:0>
4
( TMR22Output )
SCK
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSPADD)
Internal
Data Bus [SSPM<3:0>]
Read Write
Internal
Data Bus
Read Write
Shift
Clock
SSPSR Reg
SDA MSb LSb
SSPMSK Reg
SSPADD Reg
Serial Clock (SCK) Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
Serial Data Out (SDO)
three scenarios for data transmission:
Serial Data In (SDI)
Master sends useful data and slave sends dummy
Slave Select (SS)
data.
Figure 22-1 shows the block diagram of the MSSP Master sends useful data and slave sends useful
module when operating in SPI mode. data.
The SPI bus operates with a single master device and Master sends dummy data and slave sends useful
one or more slave devices. When multiple slave data.
devices are used, an independent Slave Select con-
Transmissions may involve any number of clock
nection is required from the master device to each
cycles. When there is no more data to be transmitted,
slave device.
the master stops sending the clock signal and it dese-
Figure 22-4 shows a typical connection between a lects the slave.
master device and multiple slave devices.
Every slave device connected to the bus that has not
The master selects only one slave at a time. Most slave been selected through its slave select line must disre-
devices have tri-state outputs so their output signal gard the clock and transmission signals and must not
appears disconnected from the bus when they are not transmit out any data of its own.
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 22-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave's SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master's SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
SDI bit 0
bit 7 bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
SSPIF set on 9th
Preliminary
Cleared by software Cleared by software falling edge of
SCL
BF
First byte
SSPBUF is read of data is
available
in SSPBUF
SSPOV
DS41639A-page 221
FIGURE 22-15:
DS41639A-page 222
Bus Master sends
Stop condition
SSPIF
Preliminary
BF
First byte
of data is
SSPBUF is read available
in SSPBUF
SSPOV
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
Preliminary
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
PIC16(L)F1454/5/9
DS41639A-page 223
Master sends
FIGURE 22-17:
Stop condition
Master releases
DS41639A-page 224
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSPIF
Cleared by software No interrupt after
PIC16(L)F1454/5/9
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPBUF can be
SSPBUF available on SSPBUF read any time before
next byte is loaded
ACKDT
Preliminary
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
P
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
DS41639A-page 226
R/W = 1 Automatic
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Cleared by software
BF
BF is automatically
PIC16(L)F1454/5/9
CKP
When R/W is set CKP is not
SCL is always held for not
held low after 9th SCL Set by software ACK
falling edge
ACKSTAT
Preliminary
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received
DS41639A-page 228
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSPIF
Cleared by software
BF BF is automatically
PIC16(L)F1454/5/9
ACKDT
Slave clears
ACKDT to ACK
address
Preliminary
ACKSTAT
Masters ACK
response is copied
to SSPSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
R/W
D/A
DS41639A-page 230
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
PIC16(L)F1454/5/9
SSPIF
Set by hardware Cleared by software
on 9th falling edge
BF
Data is read
Preliminary
If address matches Receive address is
SSPADD it is loaded into read from SSPBUF from SSPBUF
SSPBUF
UA
When UA = 1; Software updates SSPADD
SCL is held low and releases SCL
CKP
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
BF
Preliminary
Slave software clears
ACKDT to ACK
the received byte
UA
DS41639A-page 231
FIGURE 22-22:
DS41639A-page 232
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
PIC16(L)F1454/5/9
SSPIF
BF
Preliminary
UA
High address is loaded
UA indicates SSPADD After SSPADD is back into SSPADD
must be updated updated, UA is cleared
CKP and SCL is released
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSPCON1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
1
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop con- through SDA, while SCL outputs the serial clock. The
ditions. The Stop (P) and Start (S) bits are cleared from first byte transmitted contains the slave address of the
a Reset or when the MSSP module is disabled. Control receiving device (7 bits) and the Read/Write (R/W) bit.
of the I 2C bus may be taken when the P bit is set, or the In this case, the R/W bit will be logic 0. Serial data is
bus is Idle. transmitted eight bits at a time. After each byte is trans-
mitted, an Acknowledge bit is received. Start and Stop
In Firmware Controlled Master mode, user code conditions are output to indicate the beginning and the
conducts all I 2C bus operations based on Start and end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted con-
other communication is done by the user software tains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic 1. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a 1 to indicate the receive bit.
bit, SSPIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
Start condition detected serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
Stop condition detected
transmitted. Start and Stop conditions indicate the
Data transfer byte transmitted/received beginning and end of transmission.
Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
Repeated Start generated frequency output on SCL. See Section 22.7 Baud
Note 1: The MSSP module, when configured in Rate Generator for more detail.
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the SSP-
BUF will not be written to and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
SDA DX DX 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
TBRG
SCL
S
TBRG
DS41639A-page 240
Write SSPCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
S P
SCL held low
while CPU
responds to SSPIF
SSPIF
Cleared by software service routine
Cleared by software from SSP interrupt
Cleared by software
Preliminary
BF (SSPSTAT<0>)
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
DS41639A-page 242
ACK from Master
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
PIC16(L)F1454/5/9
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
Preliminary
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
SCL 8 9
SSPIF
Cleared in
SSPIF set at software
the end of receive Cleared in
software SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF
TBRG TBRG
SDA
SSPIF 0 0
FIGURE 22-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF 0
SSPIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPIF by software
SDA
SCL
RSEN
BCLIF
Cleared by software
S 0
SSPIF 0
TBRG TBRG
SDA
SCL
S 0
SSPIF
PEN
BCLIF
P 0
SSPIF 0
SDA
PEN
BCLIF
P 0
SSPIF 0
SSPM<3:0> SSPADD<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS = Bit is set by hardware C = User cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
REGISTER 22-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ADD<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Master mode:
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a dont care. Bit pat-
tern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a dont care.
10-Bit Slave mode Least Significant Address Byte:
TXEN
TRMT SPEN
Baud Rate Generator FOSC
n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPBRGH SPBRGL BRGH X 1 1 0 0 FIFO
FERR RX9D RCREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCIF Interrupt
RCIE
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
TX/CK
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg. Transmit Shift Reg.
Reg. Empty Flag)
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 269
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 268
SPBRGL BRG<7:0> 270*
SPBRGH BRG<15:8> 270*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 267
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23
9600 9615 0.16 12 9600 0.00 5
10417 10417 0.00 11 10417 0.00 5
19.2k 19.20k 0.00 2
57.6k 57.60k 0.00 0
115.2k
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300
1200
2400
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7
BRG Clock
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
1 1
TXEN bit
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RX/DT
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0 0
RCIF bit
(Interrupt)
Read
RCREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Upon waking from Sleep, the instruction following the 23.6.3 ALTERNATE PIN LOCATIONS
SLEEP instruction will be executed. If the Global Inter-
This module incorporates I/O pins that can be moved to
rupt Enable (GIE) bit of the INTCON register is also set,
other locations with the use of the alternate pin function
then the Interrupt Service Routine at address 004h will
register, APFCON. To determine which pins can be
be called.
moved and what their default locations are upon a
Reset, see Section 12.1 Alternate Pin Function for
more information.
PWMxDCH
PWMxOUT
to other peripherals: CWG
Latched
(Not visible to user) Output Enable (PWMxOE)
TRIS Control
Comparator R Q 0
PWMx
S Q 1
TMR2 Module
Comparator
Clear Timer,
PR2 PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by
the Timer2 prescaler to create a 10-bit time base.
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
2
GxASDLA
00
1
GxCS 0 10
1 11 GxASDLA = 01
FOSC 1
cwg_clock
CWGxDBR GxOEA
HFINTOSC
6
1
2 EN
GxIS R
= 0
TRISx CWGxA
S Q GxPOLA
async_C1OUT Input Source
async_C2OUT
PWM1OUT R Q CWGxDBF
Preliminary
PWM2OUT
6
GxOEB
EN TRISx
R = 0
GxPOLB 1
CWGxB
PIC16(L)F1454/5/9
GxASDLB = 01
00
0 10
1 11
CWG1FLT (INT pin)
GxASDFLT GxASE
Auto-Shutdown GxASDLB
async_C1OUT Source 2
S shutdown
GxASDC1 S Q D Q
async_C2OUT
GxASDC2
R Q
DS41639A-page 294
cwg_clock
PWM1
CWGxA
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 25-4: DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND
Preliminary
cwg_clock
Input Source
CWGxA
PIC16(L)F1454/5/9
source shorter than dead band
CWGxB
DS41639A-page 298
PIC16(L)F1454/5/9
EQUATION 25-1: DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock
Example:
Fcwg_clock = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = -----------------------------
Fcwg_clock
1
= -------------------
16 MHz
= 625ns
CWG Input
Source
Shutdown Source
GxASE
No Shutdown
Output Resumes
Preliminary
Shutdown
FIGURE 25-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)
PIC16(L)F1454/5/9
CWG Input
Source
Shutdown Source
GxASE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Transceiver USB
USB Clock from the D+
FS
Oscillator Module
EN
D-
Note 1: Possible optional setup for LF parts only. F parts should use internal LDO to power VUSB3V3.
2: On F devices the regulator is powered by Vdd. On LF devices the regulator is internally bypassed to Vdd.
3: 496 bytes accessible in both linear and banked data space. 16 bytes accessible in access data space only.
20BFh
Because no hardware mechanism exists to block
access to the memory, unexpected behavior can occur
if the microcontroller attempts to modify memory while
Note: Memory regions not to scale.
the SIE owns it. Also, reading the memory may
produce inaccurate data until the USB peripheral
26.4.1 BD STATUS AND CONFIGURATION returns ownership to the microcontroller.
The USB Data memory ownership and the BDnSTAT 26.4.1.2 BDnSTAT Register (CPU Mode)
bits change functionality depending on the UOWN bit
When UOWN = 0, the microcontroller core owns the
level.
BD and the other bits of the register become control
Unlike other control registers, the bit configuration for functions.
the BDnSTAT register is context sensitive determined
The Data Toggle Sync Enable (DTSEN) bit of the
by the UOWN bit. If the UOWN bit is clear, the
BDnSTAT register controls data toggle parity checking
microcontroller has the ability to modify the BD and its
and, when set, enables data toggle synchronization by
corresponding buffer. If the UOWN bit is set, the USB
the SIE. When enabled, the DTSEN checks the data
SIE has the ability to modify the BD and its
packet's parity against the value of the Data Toggle
corresponding buffer. The UOWN, BC9 and BC8 bit
Synchronization (DTS) bit. Packets incorrectly
definitions are contained within the BDnSTAT register,
synchronized are ignored and will not be written to the
regardless of the UOWN bit value.
USB RAM. The USB TRNIF bit will not be set.
26.4.1.1 Buffer Ownership However, the SIE will send an ACK token to the host to
acknowledge receipt. Refer to Table 26-1 for the effects
A simple semaphore mechanism is used to distinguish of the DTSEN bit on the SIE.
if the CPU or USB module is allowed to update the BD
and associated buffers in memory, which is shared by The Buffer Stall bit, BSTALL of the BDnSTAT register,
both. provides support for control transfers, usually one-time
stalls on Endpoint 0. It also provides support for the
The UOWN bit of the BDnSTAT register is used as a SET_FEATURE/CLEAR_FEATURE commands
semaphore to distinguish if the USB or CPU is allowed specified in Chapter 9 of the USB specification.
to update the BD and associated buffers in memory. Typically, these commands are executed by continuous
Only the UOWN bit shares functionality between the STALLs to any endpoint other than the default control
two configurations of the BDnSTAT register. endpoint.
When the UOWN bit is clear, the BD entry and buffer The BSTALL bit enables buffer stalls. Setting BSTALL
memory are owned by the microcontroller core. When causes the SIE to return a STALL token to the host if a
the UOWN bit is set, these are owned by the USB received token would use the BD in that location. The
peripheral. The BD and corresponding buffers should EPSTALL bit in the corresponding UEPn control
only be modified by the owner. However, the register is set and a STALL interrupt is generated when
BDnSTAT register can be read by either the a STALL is issued to the host. The UOWN bit remains
microcontroller or the USB, even if they are not the set and the BDs are not changed unless a SETUP
owner. token is received. In this case, the STALL condition is
Because the buffer descriptor meanings are based cleared and the ownership of the BD is returned to the
upon the source of the register update, the user must microcontroller core.
configure the basic operation of the USB peripheral The BD bits of the BDnSTAT register store the two Most
through the BDnSTAT register prior to placing Significant digits of the SIE byte count; the lower 8 digits
ownership with the USB peripheral. While still owned are stored in the corresponding BDnCNT register. See
by the microcontroller, the byte count and buffer Section 26.4.2 BD Byte Count for more information.
location registers must also be set.
26.4.1.3 BDnSTAT Register (SIE Mode) (OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB applications,
When the BD and its buffer are owned by the SIE, most
the user may want to consider the inclusion of software-
of the bits in BDnSTAT take on a different meaning. The
based address validation in their code.
configuration is shown in Register 26-6. Once the
UOWN bit is set, any data or control settings previously
26.4.4 PING-PONG BUFFERING
written there by the user will be overwritten with data
from the SIE. An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
The BDnSTAT register is updated by the SIE with the
transfer and one set for an Odd transfer. This allows the
token Packet Identifier (PID), which is stored in the PID
CPU to process one BD while the SIE is processing the
bits of the BDnSTAT register. The transfer count in the
other BD. Double-buffering BDs in this way allows for
corresponding BDnCNT register is updated. Values
maximum throughput to/from the USB.
that overflow the 8-bit register carry over to the two
Most Significant digits of the count, BD bits of the The USB module supports four modes of operation:
BDnSTAT register. No ping-pong support
Ping-pong buffer support for OUT Endpoint 0 only
26.4.2 BD BYTE COUNT
Ping-pong buffer support for all endpoints
The byte count represents the total number of bytes
Ping-pong buffer support for all other Endpoints
that will be transmitted during an IN transfer. After an IN
except Endpoint 0
transfer, the SIE will return the number of bytes sent to
the host. The ping-pong buffer settings are configured using the
PPB bits in the UCFG register.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and The USB module keeps track of the Ping-Pong Pointer
stored in USB RAM. After an OUT transfer, the SIE will individually for each endpoint. All pointers are initially
return the actual number of bytes received. If the reset to the Even BD when the module is enabled. After
number of bytes received exceeds the corresponding the completion of a transaction (UOWN cleared by the
byte count, the data packet will be rejected and a NAK SIE), the pointer is toggled to the Odd BD. After the
handshake will be generated. When this happens, the completion of the next transaction, the pointer is
byte count will not be updated. toggled back to the Even BD and so on.
The 10-bit byte count is distributed over two registers. The Even/Odd status of the last transaction is stored in
The lower 8 bits of the count reside in the BDnCNT reg- the PPBI bit of the USTAT register. The user can reset
ister. The upper two bits reside in the BC bits of the all Ping-Pong Pointers to Even using the PPBRST bit.
BDnSTAT register. This represents a valid byte range Figure 26-5 shows the four different modes of opera-
of 0 to 1023. tion and how USB RAM is filled with the BDs. BDs have
a fixed relationship to a particular endpoint depending
26.4.3 BD ADDRESS VALIDATION on the buffering configuration. The mapping of BDs to
endpoints is detailed in Table 26-2. This relationship
The BD Address register pair contains the starting RAM
also means that gaps may occur in the BDT if end-
address location for the corresponding endpoint buffer.
points are not enabled contiguously. This theoretically
No mechanism is available in hardware to validate the
means that the BDs for disabled endpoints could be
BD address.
used as buffer space. In practice, users should avoid
If the value of the BD address does not point to an using such spaces in the BDT unless a method of vali-
address in the USB RAM, or if it points to an address dating BD addresses is implemented.
within another endpoint's buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
Mode 3
Mode 0 Mode 1 Mode 2
Endpoint (Ping-Pong on all other EPs,
(No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs)
except EP0)
SOFIF
SOFIE
BTSEF
BTSEE TRNIF USBIF
TRNIE
BTOEF
BTOEE
IDLEIF
DFN8EF IDLEIE
DFN8EE UERRIF
CRC16EF UERRIE
CRC16EE
CRC5EF STALLIF
STALLIE
CRC5EE
PIDEF
PIDEE ACTVIF
ACTVIE
URSTIF
URSTIE
Control Transfer(1)
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
The calculated value should be considered an approximation and additional guardband or application-specific prod-
uct testing is recommended. The transceiver current is in addition to the rest of the current consumed by the
microcontroller.
Device
Configuration
To other Interfaces (if any)
Interface Interface
Note 1: This bit cannot be set if the USB module does not have an appropriate clock source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values
must be preconfigured prior to enabling the module.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
REGISTER 26-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
3: If these bits are set, USB communication may not work. Hence, these bits should always be maintained as 0.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
27.2 Low-Voltage Programming Entry Another connector often found in use with the PICkit
Mode programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 27-2.
The Low-Voltage Programming Entry mode allows the
PIC Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to 1, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to 0.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.5 MCLR for more
information.
The LVP bit can only be reprogrammed to 0 by using
the High-Voltage Programming mode.
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
OPCODE only
13 0
OPCODE
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP No Operation 1 00 0000 0000 0000
OPTION Load OPTION_REG register with W 1 00 0000 0110 0010
RESET Software device Reset 1 00 0000 0000 0001
SLEEP Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm kkkk
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk 1nmm Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 kkkk 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk 2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register f are shifted
one bit to the right through the Carry
flag. A 0 is shifted into the MSb. If d is
0, the result is placed in W. If d is 1,
the result is stored back in register f.
0 register f C
Before Instruction
W = 0x07
After Instruction
W = value of k8
2.7
2.3
0 10 20 40 48
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator modes supported frequencies.
3.6
2.7
1.8
0 10 20 40 48
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator modes supported frequencies.
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2) TPOR(3)
145 A 5.0
*
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
1600 A 5.0
D019A 750 A 3.0 FOSC = 20 MHz
ECH mode
D019A 1400 A 3.0 FOSC = 20 MHz
1600 A 5.0 ECH mode
D019B 6 A 1.8 FOSC = 32 kHz ECL mode
8 A 3.0
D019B 11 A 2.3 FOSC = 32 kHz ECL mode
15 A 3.0
18 A 5.0
D019C 15 A 1.8 FOSC = 500 kHz ECL mode
20 A 3.0
D019C 35 A 2.3 FOSC = 500 kHz ECL mode
45 A 3.0
55 A 5.0
D020 150 A 1.8 FOSC = 4 MHz EXTRC mode (Note 3)
280 A 3.0
D020 230 A 2.3 FOSC = 4 MHz EXTRC mode (Note 3)
310 A 3.0
370 A 5.0
*
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
280 A 5.0
D027 7 A 1.8 Comparator, Low-Power mode
8 A 3.0 (Note 1)
Param
Sym Characteristic Min Typ Max Units Conditions
No.
D313 VUSB USB Voltage 3.0 3.6 V Voltage on VUSB3V3 pin must be
in this range for proper USB
operation
D314 IIL Input Leakage on pin 1 A VSS VPIN VDD pin athigh
impedance
D315 VILUSB Input Low Voltage for USB 0.8 V For VUSB3V3 range
Buffer
D316 VIHUSB Input High Voltage for USB 2.0 V For VUSB3V3 range
Buffer
D318 VDIFS Differential Input Sensitivity 0.2 V The difference between D+ and
D- must exceed this value while
VCM is met
D319 VCM Differential Common Mode 0.8 2.5 V
Range
D320 ZOUT Driver Output Impedance(1) 28 44
D321 VOL Voltage Output Low 0.0 0.3 V 1.5 kload connected to 3.6V
D322 VOH Voltage Output High 2.8 3.6 V 1.5 kload connected to ground
Note 1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors,
capacitors or magnetic components are necessary on the D+/D- signal paths between the
PIC16(L)F1454/5/9 family device and USB cable.
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc CLKIN
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Pin CL
VSS
Q4 Q1 Q2 Q3 Q4 Q1
CLKIN
OS02 OS12 OS11
OS03
CLKOUT
(CLKOUT Mode)
OS01 FOSC External CLKIN Frequency(1) DC 0.5 MHz EC Oscillator mode (low)
DC 4 MHz EC Oscillator mode (medium)
DC 20 MHz EC Oscillator mode (high)
OS02 TOSC External CLKIN Period(1) 31.25 ns EC mode
OS03 TCY Instruction Cycle Time(1) 125 DC ns TCY = FOSC/4
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at min values with an external clock applied to CLKIN pin. When an external
clock input is used, the max cycle time limit is DC (no clock) for all devices.
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage 7.5 60 mV High Power mode
VICM = VDD/2
CM02 VICM Input Common Mode Voltage 0 VDD V
CM04A Response Time Rising Edge 400 800 ns High-Power mode
(Note 1)
CM04B Response Time Falling Edge 200 400 ns High-Power mode
(Note 1)
TRESP
CM04C Response Time Rising Edge 1200 ns Low-Power mode
(Note 1)
CM04D Response Time Falling Edge 550 ns Low-Power mode
(Note 1)
CM05 TMC2OV Comparator Mode Change to 10 s
Output Valid*
CM06 CHYSTER Comparator Hysteresis 65 mV Note 2
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
DAC01* CLSB Step Size VDD/32 V
DAC02* CACC Absolute Accuracy 1/2 LSb
DAC03* CR Unit Resistor Value (R) 5K
DAC04* CST Settling Time(1) 10 s
* These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<4:0> transitions from 0000 to 1111.
CK
US121 US121
DT
US120 US122
CK
US125
DT
US126
SS
SP70
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
PIC16F1454
-E/P e3
1220123
PIC16F1455
-E/SL e3
1220123
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
XXXXXXXX F1454EST
YYWW 1220
NNN 123
PIC16
F1455
PIN 1 PIN 1
E/ML e3
220123
XXXXXXXXXXXXXXXXX PIC16F1459
XXXXXXXXXXXXXXXXX -E/P e3
YYWWNNN 1220123
PIC16F1459
-E/SO e3
1220123
PIC16F1459
-E/SS e3
1220123
PIC16
PIN 1 PIN 1
F1459
E/ML e3
220123
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Revision A (06/2012)
Initial release.
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
Package:(2) ML = QFN 4x4 Note 1: Tape and Reel identifier only appears in
P = Plastic DIP the catalog part number description. This
SS = SSOP identifier is used for ordering purposes and
ST = TSSOP is not printed on the device package.
SO = SOIC 20-Lead Check with your Microchip Sales Office
SL = SOIC 14-Lead for package availability with the Tape and
Reel option.
2: Small form-factor packaging options may
Pattern: QTP, SQTP, Code or Special Requirements be available. Please check
(blank otherwise) www.microchip.com/packaging for small
form-factor package availability, or contact
your local sales office.