International Journal of Applied Engineering Research

ISSN 0973-4562 Volume 9, Number 24 (2014) pp. 23985-24001

Research India Publications
http://www.ripublication.com

Worst Case Test Vector Exposed To Total Dose In

Combinational ASICs

J. ROBERT THEIVADAS1, V. RANGANATHAN 2

(1Research Scholar, Anna University, Chennai 600025)

2
( Sree Sastha Institute of Engineering and Technology, Chennai 600123)
E-mail: roberttheivadas@gmail.com ; drvrangan@gmail.com

Abstract

The method reviews the fault model and worst case test vector exposed to total
dose in combinational ASICs. Due to total dose effects logic failure occur
which results in negative threshold voltage. The short channel and long
channel failure analysis is obtained to find the negative threshold voltage shift.
The fault model is abstracted to model logic failure induced in three generic
static CMOS gate (INV, NOR and NAND). To obtain the fault model select
irradiation and post irradiation input vectors that satisfy the condition for
excitation and manifestation of logic failure and sensitivity to logic failure
induced by total dose is determined by excitation condition of gates and
equivalent width ratio of long channel and short channel transistor. The
sensitivity of the fault model is validated using spice simulation. The
sensitivity of the gate to logic failure depends on logic input combination (I,
P), type of gate used and width of the transistor. The worst case test vectors
are identified by failure analysis of each gate and sensitivity of each gate
induced to total dose for logic failure. The worst case test vectors are validated
using
ATPG tools. The test vectors are selected such that it satisfy the fault model,
excitation condition and manifest fault to primary output. The methodology is
independent of the design tool and process technology.

Key Words : worst case test vector, total dose, irradiation, post irradiation,
sensitivity.
23986 J. ROBERT THEIVADAS, V. RANGANATHAN

Introduction
The paper reviews about the total dose effects in combinational CMOS circuit [1].
Total dose effects results in logic failure leads to damage in the circuit. Due to deep
submicron technology, the process used in the manufacture of integrated circuits
themselves may produce ionizing radiation [6]. Total dose is the cumulative ionizing
radiation that an electronic device receives over a specified interval of time [3]. The
total dose results in slow gradual degradation of device performance. The maximum
degradation [5] results in negative threshold voltage shift in NMOS which is difficult
to switch off even at zero voltage and positive threshold voltage shift in PMOS which
is difficult to switch on. These leads to device failure in CMOS circuits [3]. In order
to find the device failure due to total ionizing dose and to develop the cell level logic
fault model taking different factors into account contributing the sensitivity of each
cell [1].
The total dose testing standard, MIL-STD-883, method 1019, emphasizes that the
worst case test vector are applicable in total dose testing of VLSI devices because it is
difficult to identify using transistor level SPICE simulation [7,8]. The development of
methodology of identifying worst case test vector for logic faults induced by total
dose in CMOS combinational microcircuits consisting of INV, NOR and NAND is
extended to identify worst case test vector for cell based ASIC combinational circuits
[9, 10, 11, 12, 13]. The paper reviews about the methodology for identifying worst
case test vector for logic failure induced by total dose in combinational cell based
ASIC. The cell level fault model is identified by sensitivity of each cell. The fault
model is validated using transistor level SPICE simulation. The worst case test
vectors are validated using ATPG tools such as Mentor Graphics Fast Scan. The test
vectors are selected such that it satisfy the fault model, excitation condition and
manifest fault to primary output [1].The previous methodology in finding fault model
and worst case test vector for logic failure induced by total dose in combinational
circuit of cell based ASICs is developed for small number of inputs [1]. Then the
methodology is extended for finding fault model and worst case test vector for
leakage current failures induced by total dose in ASICs with the large number of
inputs was developed [16]. And the research extended to CMOS processes exhibiting
field oxide leakage [17]. With the development of methodology total dose induced in
deep submicron SRAM is practically analyzed [18]. Then the fault model and worst
case test vector of sequential circuit exposed to total dose is experimentally validated
using HDL design and it is simulated using SPICE simulation and ADK design kit 3.1
[19]. Then methodology is extended to find the delay failure in ASICs design [20].
The extension of methodologies results in efficient analysis of fault model, worst case
test vector for logic failure, delay failure and leakage failure for sequential circuit,
combinational circuit and SRAM.
The implementation of methodology on combinational circuit of a 88 multiplier
using RTL verilog. In 88 multiplier, 20 different types of full adders are used with
the logic optimization by rearranging Boolean equation [14]. From the analysis the
optimized equations of full adder are chosen to construct the 88 multiplier. The logic
optimized multiplier based adders are incorporated in existing adders like ripple carry
adder carry look-ahead adder, carry skip adder, carry select adder, carry increment
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23987

adder and carry save adder and its performance is analyzed in terms of area and total
dose of individual gates used in full adders to excite and manifest the logic failure by
obtaining the sensitivity. The 88 multiplier is incorporated using 20 different types
of full adder by rearranging Boolean equation with XOR, NAND, AND, OR, NOR,
NOT, XNOR, MUX, etc.., and the logic failure of multiplier is analyzed by obtaining
the total dose of each gates with the value of sensitivity. Final determination of the
experiment is to find the multipliers which respond to high sensitivity to total dose
and low sensitivity to the total dose in various gates of full adders [15].
The paper explains logic failure analysis in CMOS inverter in section I, section II
explains fault model, worst case test vector is explained in section III, flow graph of
methodology is shown in section IV, implementation of multiplier using adders is
explained in section V, simulation result is explained in section VI and the
methodology is concluded in section VI.

Logic Failure Ananlysis In Cmos Inverter

Consider CMOS inverter in order to analyze logic failure exposed to total dose which
results in negative threshold shift of the NMOS transistor and minimal shifts for
PMOS and voltage transfer characteristics shifts to left [21]. The negative shift in
voltage transfer characteristic is determined clearly when irradiation input bias is high
or I=1 is more significant than the shifts when I=0. The switching voltage (V s) gain is
very high. Therefore consider a total dose induced logic fault at the output of the
inverter when Vs 0 due to total dose.

Long Channel Failure Anaysis

In MOS transistor long channel models is given by,
Vs = (VDD + Vtp +r. Vtn) / (1 + r) (1)
where Vs is the switching voltage, = ( / . / , VDD is the supply
voltage [2]. The MOS transistor parameters are k' is the current gain, Vt is the
threshold voltage, W is the channel width and subscript n and p represents NMOS and
PMOS transistor respectively.
If logic failure occurs, Vs =0 , r' is given by
= ( / . / =- (VDD+Vtp)/Vtn Vtn is the only parameter that shift to
negative region when transistor is exposed to total dose while other parameter
undergoes negligible shifts, So the condition for logic failure is given by,
= ( / . / =- (VDD+Vtp)/Vtn
= / = -A/ Vtn (2)
where
= ( . is a constant which depends on supply voltage and process
23988 J. ROBERT THEIVADAS, V. RANGANATHAN

technology. This represents that CMOS inverters with higher r value has less negative
threshold shifts and consequently will logical fails at less total dose levels.

Short Channel Logic Failure

In MOS transistor short channel models is given by,

Vs=((VDD+Vtp+VDSATp/2) + r'. (Vtn+VDSATn/2))/ (1+r') (3)

where VDSATn and VDSATp are the saturation voltages for both NMOS and PMOS
transistors respectively.

r'= vsatn Wn/vsatp Wp (4)

where vsatn and vsatp are the saturation velocities of majority carriers in NMOS and
PMOS transistors respectively. The logic failure for CMOS inverters occurs when
switching voltage is zero and the condition for logic failure is given in equation (3)
and (6) and sensitivity of short channel failure is proportional to

r = Wn / Wp = - A/(Vtn+VDSATn/2) (5)

where A=( vsatn/vsatp)(VDD+Vtp+VDSATp/2) is a constant that depends on supply

voltage and the process technology. In both analysis sensitivity depends on Wn / Wp ,
but sensitivity of long channel failure seems to be affected more than short channel
failure. In both cases, NMOS transistor that has high bias or logic 1 should be given
as input at its irradiation (I=1) which undergoes maximum degradation. The post
irradiation (P=0) should be logic 0 that will turn off the NMOS transistor and manifest
the logic failure. For testing the CMOS transistors the test vectors should excite and
manifest the logic fault at the output. In CMOS inverters test vectors for excitation
and manifestation of fault is I=1 and P=0. More detailed analysis is obtained to study
logic failure and identification of test vectors for different types of cell.

Fault Model
Fault model is an abstraction of logic failure at certain level of circuit representation
that is performed to simplify the process of generating test vectors. The detailed
description of fault model logic failure in three generic static CMOS gates (INV,
NAND and NOR) is studied [9]. The dose level varies from gate to gate depending on
the sensitivity of the gate in order to manifest the fault. The irradiation and post
irradiation input vectors are selected such that it should satisfy the excitation and
manifestation condition. The excitation and manifestation condition for CMOS gate
are
1) In CMOS gate, NMOS transistor has a stuck on fault excited condition; i.e.,
I/P=1/0.
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23989

2) The connection path of NMOS and PMOS pair which has no stuck on NMOS
transistor between VDD and ground is established. i.e., the series transistor should be
ON and Parallel transistor should be OFF.
3) The SA-0 should be manifested at the output of the gate.
Using the above three rules the model of excitation condition E for various gates.
E equals 1 if it satisfy above three condition, otherwise E=0. The irradiation test
vectors are I=[I1, I2,I3,Im] and Ij E {0,1). The post irradiation input vectors are
P=[P1,P2,P3,..Pm] and Pj E {0,1}. The excitation condition for NOR-2 gates can be
expressed as,
E(I,P)nor-2=(I1+I2)P1P2. (7)
The sensitivity of gates is proportional to the equivalent r ratio. In order to
evaluate the equivalent r ratio consider the equivalent channel width and equal
channel length for all transistor.
The equivalent r ratio for long channel is given
by,r(I, P) = 1/ ( = 1,2)
i i
W N and W P are the channel width of the NMOS and PMOS transistor respectively.

Cell S(I,P) IP Cell S(I,P) IP Cell S(I,P) IP

NOR-3 1.573 101010 INV-1 0.745 10 XOR-2 0.620 1000

NOR-3 1.285 101000 NAND-2 0.745 011 AND-3 0.577 100101
OR-3 1.285 101000 XOR-2 0.745 1 NAND-3 0.577 1011
NOR-2 1.241 1010 MUX-21 0.745 1101 AND-2 0.456 1010
OR-2 1.241 1010 MUX-21 0.745 100000 NAND-2 0.456 1010
NAND-2 0.911 110 MUX-21 0.745 0010 XNOR-2 0.439 1010
NAND-2 0.911 101 MUX-21 0.745 110 XOR-2 0.439 1010
NOR-2 0.877 1000|0010 AND-2 0.645 101 NAND-3 O.412 10101
XNOR-2 0.877 011 XNOR-2 0.620 1000 AND-3 0.408 101001
XOR-2 0.877 011 XNOR-2 0.620 110 NAND-3 0.333 101010
AND-3 0.745 010101 XOR-2 0.620 101 AND-3 0.333 101010

Table-1: Sensitivity of gates

For short channel the equivalent r ratio is given by,

r(I,P) nor-2= IiPiWiN 1/WiP (i=1,2)
The sensitivity to logic failure induced by total dose is expressed as,
S(I,P) ) nor-2= E(I,P) ) nor-2 r(I,P) ) nor-2
The E (I, P) is the excitation condition of the gate and r(I,P) is the equivalent
width ratio for long channel and short channel transistor. The sensitivity of the gate
depends on both logic input combination (I, P) and the width of the transistor inside
the gate. Hence sensitivity is affected highly by long channel; fault model is obtained
and validated in long channel failure analysis.
23990 J. ROBERT THEIVADAS, V. RANGANATHAN

Worst Case Test Vector

The methodology for identification of worst case test vectors for logic failure induced
by total dose in cell based ASICs is obtained by failure analysis of each cell and
develop fault model. The fault models are validated using SPICE simulation with
transistor parameter from target process and transistor parametric degradation from
total dose experiment [21].
The sensitivity of the gate is ranked according to their value written in ascending
order and insert stuck at fault at its output in cell which has maximum sensitivity.
Identification of input vectors that satisfy the fault model and its corresponding
excitation conditions that manifest the fault at the primary outputs of the circuit under
test is obtained.

Flow Of Methodology
TOTAL DOSE IN COMBINATIONAL
ASICs- GATES SUFFER FROM LOGIC
FAILURE

FAULT MODEL (SATISFY EXCITATION

AND MANIFESTATION CONDITION)

WORST CASE TEST VECTORS

(IRRADIATION AND POST IRRADIATION
INPUT VECTORS)

SENSITIVITY OF GATES (DEPENDS ON

EXCITATION CONDITION AND
EQUIVALENT r RATIO)

DETERMINE GATES SUFFERING FROM

HIGH AND LOW SENSITIVITY

Fig 1: Procedure for finding logic failure induced by total dose

Types Of Full Adders Used In 88 Multiplier

The implementation of methodology on combinational circuit of a 88 multiplier
using RTL verilog as shown in Fig.22. In 88 multiplier, 20 different types of full
adders are used with the logic optimization by rearranging Boolean equation. From
the analysis the optimized equations of full adder are chosen to construct the 88
multiplier. The logic optimized multiplier based adders are incorporated in existing
adders like ripple carry adder carry look-ahead adder, carry skip adder, carry select
adder, carry increment adder and carry save adder and its performance is analyzed in
terms of area and total dose of individual gates used in full adders to excite and
manifest the logic failure by obtaining the sensitivity. The 88 multiplier is
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23991

incorporated using 20 different types of full adder by rearranging Boolean equation

with XOR, NAND, AND, OR, NOR, NOT, XNOR, MUX, etc.., and the logic failure
of multiplier is analyzed by obtaining the total dose of each gates with the value of
sensitivity. Final determination of the experiment is to find the multipliers which
respond to high sensitivity to total dose and low sensitivity to the total dose in various
gates of full adders.

Type-1 Multiplier
The multiplier uses full adder as shown in Fig.2. The gates used in TYPE-1 multiplier
are INV-1, XNOR-2, AND-2, OR-3, XOR-2 and OR-2.

Fig.2. TYPE-1 MULTIPLIER

TYPE-2 MULTIPLIER
The multiplier uses full adder as shown in Fig.3. The gates used in TYPE-2 multiplier
are XOR-2, AND-2, and OR-2.

Fig.3. TYPE-2 MULTIPLIER

TYPE-3 MULTIPLIER
The multiplier uses full adder as shown in Fig.4. The gates used in TYPE-3 multiplier
are XNOR-2, AND-2, OR-3,INV-1, XOR-2 and OR-2.
23992 J. ROBERT THEIVADAS, V. RANGANATHAN

Fig.4. TYPE-3 MULTIPLIER

TYPE-4 MULTIPLIER
The multiplier uses full adder as shown in Fig.5. The gates used in TYPE-4 multiplier
are XNOR-2, INV-1, AND-2, OR-2 and XOR-2.

Fig. 5. TYPE-4 MULTIPLIER

TYPE-5 MULTIPLIER
The multiplier uses full adder as shown in Fig.6. The gates used in TYPE-5 multiplier
are XOR-2, AND-2 and OR-2.

Fig. 6. TYPE-5 MULTIPLIER

TYPE-6 MULTIPLIER
The multiplier uses full adder as shown in Fig.7. The gates used in TYPE-6 multiplier
are XOR-2, NOR-2, NAND-2, XNOR-2, INV-1, AND-2 and OR-2.
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23993

Fig. 7. TYPE-6 MULTIPLIER

TYPE-7 MULTIPLIER
The multiplier uses full adder as shown in Fig.8. The gates used in TYPE-7 multiplier
are XNOR-2, NAND-3, NAND-2, INV-1, XOR-2, AND-2 and OR-2.

Fig. 8. TYPE-7 MULTIPLIER

TYPE-8 MULTIPLIER
The multiplier uses full adder as shown in Fig.9. The gates used in TYPE-8 multiplier
are XNOR-2, NAND-2, NAND-3, INV-1, XOR-2, AND-2 and OR-2.

Fig. 9. TYPE-8 MULTIPLIER

TYPE-9 MULTIPLIER
The multiplier uses full adder as shown in Fig.10. The gates used in TYPE-9
multiplier are XOR-2, NAND-2, NAND-3, OR-2 and AND-2.
23994 J. ROBERT THEIVADAS, V. RANGANATHAN

Fig. 10. TYPE-9 MULTIPLIER

TYPE-10 MULTIPLIER
The multiplier uses full adder as shown in Fig.11. The gates used in TYPE-10
multiplier are XOR-2, MUX-21, AND-2 and OR-2.

Fig. 11. TYPE-10 MULTIPLIER

TYPE-11 MULTIPLIER
The multiplier uses full adder as shown in Fig.12. The gates used in TYPE-11
multiplier are INV-1, XNOR-2, MUX-21, XOR-2, OR-2 and AND-2.

Fig. 12. TYPE-11 MULTIPLIER

TYPE-12 MULTIPLIER
The multiplier uses full adder as shown in Fig.13. The gates used in TYPE-12
multiplier are XOR-2, XNOR-2, MUX-21, AND-2 and OR-2.
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23995

Fig. 13 TYPE-12 MULTIPLIER

TYPE-13 MULTIPLIER
The multiplier uses full adder as shown in Fig.14. The gates used in TYPE-13
multiplier are XOR-2, AND-2, INV-1, AND-3, OR-2 and MUX-21.

Fig. 14. TYPE-13 MULTIPLIER

TYPE-14 MULTIPLIER
The multiplier uses full adder as shown in Fig.15. The gates used in TYPE-14
multiplier are XNOR-2, INV-1, AND-2, AND-3, OR-2, MUX-21 and XOR-2.

Fig. 15. TYPE-14 MULTIPLIER

TYPE-15 MULTIPLIER
The multiplier uses full adder as shown in Fig.16. The gates used in TYPE-15
multiplier are NAND-2, XOR-2, AND-2 and OR-2.
23996 J. ROBERT THEIVADAS, V. RANGANATHAN

Fig. 16. TYPE-15 MULTIPLIER

TYPE-16 MULTIPLIER
The multiplier uses full adder as shown in Fig.17. The gates used in TYPE-16
multiplier are NOR-2, XOR-2, AND-2 and OR-2.

Fig. 17. TYPE-16 MULTIPLIER

TYPE-17 MULTIPLIER
The multiplier uses full adder as shown in Fig.18. The gates used in TYPE-17
multiplier are XOR-2, NAND-2, NOR-2, NAND-3, INV-1, AND-2 and OR-2.

Fig. 18. TYPE-17 MULTIPLIER

TYPE-18 MULTIPLIER
The multiplier uses full adder as shown in Fig.19. The gates used in TYPE-18
multiplier are XNOR-2, INV-1, NOR-2, OR-2, XOR-2 and AND-2.
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23997

Fig. 19. TYPE-18 MULTIPLIER

TYPE-19 MULTIPLIER
The multiplier uses full adder as shown in Fig.20. The gates used in TYPE-19
multiplier are XNOR-2, NOR-2, NAND-2, INV-1, NAND-3, XOR-2, OR-2 and
AND-2.

Fig. 20. TYPE-19 MULTIPLIER

TYPE-20 MULTIPLIER
The multiplier uses full adder as shown in Fig.21. The gates used in TYPE-20
multiplier are XOR-2, INV-1, NOR-2, XNOR-2, OR-2 and AND-2.

Fig. 21. TYPE-20 MULTIPLIER

23998 J. ROBERT THEIVADAS, V. RANGANATHAN

HIGH SENSITIVITY LOW SENSITIVITY

MULTIPLIER GATES USED
GATE GATE

TYPE-1 INV-1,XNOR-2,AND-2,OR-3, XOR-2,OR-2 OR-3=1.285 XOR-2=0.439

TYPE-2 XOR-2,AND-2, OR-2 OR-2=1.241 XOR-2=0.439

TYPE-3 XNOR-2,AND-2,OR-3,INV-1, XOR-2,OR-2 OR-3=1.285 XOR-2=0.439

TYPE-4 XNOR-2,INV-1,AND-2,OR-2, XOR-2 OR-2=1.241 XOR-2=0.439

TYPE-5 XOR-2,AND-2,OR-2 OR-2=1.241 XOR-2=0.439

XOR-2,NOR-2,NAND-2, XNOR-2,INV-1,AND-
TYPE-6 OR-2,NOR-2=1.241 XOR-2=0.439
2,OR-2

XNOR-2,NAND-3,NAND-2, INV-1,XOR-
TYPE-7 OR-2=1.241 NAND-3=0.333
2,AND-2,OR-2

XNOR-2,NAND-2,NAND-3, INV-1,XOR-
TYPE-8 OR-2=1.241 NAND-3=0.333
2,AND-2,OR-2

TYPE-9 XOR-2,NAND-2,NAND-3, OR-2,AND-2 OR-2=1.241 NAND-3=0.333

TYPE-10 XOR-2,MUX-21,AND-2,OR-2 OR-2=1.241 AND-2=0.456

TYPE-11 INV-1,XNOR-2,MUX-21, XOR-2,OR-2,AND-2 OR-2=1.241 AND-2=0.456

TYPE-12 XOR-2,XNOR-2,MUX-21, AND-2,OR-2 OR-2=1.241 XOR-2=0.439

TYPE-13 XOR-2,AND-2,INV-1,AND-3, OR-2,MUX-21 OR-2=1.241 AND-3=0.333

XNOR-2,INV-1,AND-2, AND-3,OR-2,MUX-
TYPE-14 OR-2=1.241 AND-3=0.333
21,XOR-2

TYPE-15 NAND-2,XOR-2,AND-2,OR-2 OR-2=1.241 XOR-2=0.439

TYPE-16 NOR-2,XOR-2,AND-2,OR-2 OR-2,NOR-2=1.241 XOR-2=0.439

XOR-2,NAND-2,NOR-2, NAND-3,INV-1,AND-
TYPE-17 OR-2,NOR-2=1.241 NAND-3=0.333
2,OR-2

TYPE-18 XNOR-2,INV-1,NOR-2,OR-2, XOR-2,AND-2 NOR-2,OR-2=1.241 XOR-2=0.439

XNOR-2,NOR-2,NAND-2, INV-1,NAND-
TYPE-19 OR-2,NOR-2=1.241 NAND-3=0.333
3,XOR-2,OR-2, AND-2

TYPE-20 XOR-2,INV-1,NOR-2,XNOR-2, OR-2,AND-2 NOR-2,OR-3=1.241 XOR-2=0.439

Table-2: Different Types Of Multiplier With Gates Used, High Sensitivity And Low
Sensitivity Of Gates
Worst Case Test Vector Exposed To Total Dose In Combinational ASICs 23999

Fig 22: 88 Multiplier Using Full Adder and Half Adder Circuit

Simuation Results
The implementation of methodology is done in 88 multiplier using RTL verilog as
shown in Fig.22. Hence the multiplier is built using 20 different Boolean expressions
(logic construction) to implement full adder. From the analysis the optimized
equations of full adder are chosen to construct the 88 multiplier. The logic optimized
multiplier based adders are incorporated in existing adders like ripple carry adder
carry look-ahead adder, carry skip adder, carry select adder, carry increment adder
and carry save adder and its performance is analyzed in terms of area and total dose of
individual gates used in full adders to excite and manifest the logic failure by
obtaining the sensitivity. The 88 multiplier is incorporated using 20 different types
of full adder by rearranging Boolean equation with XOR, NAND, AND, OR, NOR,
NOT, XNOR, MUX, etc.., and the logic failure of multiplier is analyzed by obtaining
the total dose of each gates with the value of sensitivity. The tabular column clearly
explains the sensitivity of each gate (Table-1). The Table-2 clearly determines the
multiplier with low sensitivity of the gate and high sensitivity of the gate. The final
declaration is to determine the multiplier which is affected by total dose with high
sensitivity and low sensitivity. From Table-1 it clearly shows that the gate which
suffers from high sensitivity is NOR-3 and gate which suffers from low sensitivity is
24000 J. ROBERT THEIVADAS, V. RANGANATHAN

AND-3. So in 20 types of multiplier TYPE-1 and 3 multiplier suffers from high

sensitivity and TYPE- 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20
multiplier suffers from low sensitivity shown in Table-2. The output of the multiplier
with worst case test vector is shown in Table-3.

WCTV I 1011101111010111
P 000001100110110
OUTPUT FAULT 1001110100001101
FREE
FAULTY 0000001010010100

Table-3 (Worst Case Test Vector For 88 Multiplier)

Conclusions
The methodology that identifies fault model and worst case test vectors for logic
failures induced by total dose in combinational circuits of cell based CMOS ASICs.
The major advantage of the methodology is independent of the design tools and the
process technology and uses the same synthesis, test vector generation and simulation
tools. The identification of fault model is validated using SPICE simulation and worst
case test vectors are validated using ATPG tools such as Mentor Graphics Fast Scan.
The sensitivity of gates is obtained to determine logic failure exposed to total dose.

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24002 J. ROBERT THEIVADAS, V. RANGANATHAN