The document provides the schedule for Assessment-1 exams for the M.Tech VLSI System semester 1 program at the National Institute of Technology in Tiruchirappalli, India. It lists the 6 courses to be assessed between September 18-20, 2017, including the course code, name, date, and time for each exam. All exams will take place in venue LH-114.
The document provides the schedule for Assessment-1 exams for the M.Tech VLSI System semester 1 program at the National Institute of Technology in Tiruchirappalli, India. It lists the 6 courses to be assessed between September 18-20, 2017, including the course code, name, date, and time for each exam. All exams will take place in venue LH-114.
The document provides the schedule for Assessment-1 exams for the M.Tech VLSI System semester 1 program at the National Institute of Technology in Tiruchirappalli, India. It lists the 6 courses to be assessed between September 18-20, 2017, including the course code, name, date, and time for each exam. All exams will take place in venue LH-114.
Schedule for Assessment- 1 M.Tech. VLSI SYSTEM- SEM-I (2017-2018)
VENUE: LH-114
COURSE COURSE NAME DATE TIME
CODE EC653 Basics of VLSI 18-09-2017 09:30 -10:30 FN MA617 Graph Theory and Discrete Optimization 18-09-2017 02:30 -03:30 AN EC802 Modeling and synthesis with Verilog HDL 19-09-2017 09:30 -10:30 FN EC803 Digital Signal processing Structures for VLSI 19-09-2017 02:30 -03:30 AN EC651 Analog IC Deign 20-09-2017 09:30 -10:30 FN EC801 Digital System Design 20-09-2017 02:30 -03:30 AN
Class Committee Chairperson Head of the Department
(Cambridge IISc Series) A. K. Nandakumaran, P. S. Datti - Partial Differential Equations - Classical Theory With A Modern Touch (Cambridge IISc Series) - Cambridge University Press (2020)