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Simulation of Closed Loop STATCOM For Power Quality Improvement Description
Simulation of Closed Loop STATCOM For Power Quality Improvement Description
Description:
A VSC based STATCOM in implemented in a two-machine transmission system with the sending and
receiving end voltages of 220 kV (RMS) and their phase angle difference () is 30.
During steady-state operation the STATCOM, control system keeps the fundamental component of the
VSC voltage in phase with the system voltage. If the voltage generated by the VSC is higher (or lower)
than the system voltage, the STATCOM generates (or absorbs) reactive power. The amount of reactive
power depends on the VSC voltage magnitude and on the transformer leakage reactance. The
fundamental component of VSC voltage is controlled by varying the DC bus voltage. In direct
approach, the internal PWM technique is used for output voltage control of the converter in which case
the dc voltage is kept constant (by the control of the angle).
Modelling of STATCOM:
The basic building block of a two level VSC based STATCOM is shown in figure below.
1 3 5
2 2 2
Sa1 Sb1 Sc1
Van 0.2 [ohm] 2.8 [mH]
Ia
Ean
6000.0 [uF]
Vbn 0.2 [ohm] 2.8 [mH]
Ib
Ebn
Vdc
Vcn 0.2 [ohm] 2.8 [mH]
Ic
Ecn
4 6 2
2 2 2
Sa12 Sb12 Sc12
The VSC terminal voltages , and (measured with respect to the source neutral) can be
obtained from the following equations
Hence, we get
and
The voltages and current in the AC circuits are transformed to a synchronously rotating reference frame
by using following transformation
[ ] [ ]
Using this transformation the circuit equations in d-q variables are given as
Where and are then translated into phase and magnitude to produce the modulating waveform.
PSCAD Implementation:
deg
deg
bus1
Kv
Hz
Kv
Hz
bus2
210 -10 49 210 -40 49
221.6 0 50 220 -30 50
A
V
#1
20 [ohm]
#2
0.1 [H]
100.0 [MW] 10.0 [MVAR] 300.0 [MW] 10.0 [MVAR]
Eab
Timed
Fault
ABC->G Logic
Ea Eb Ec
Vm
1 Va
*
Vm 0.004545 3 2 1 G *
A D
Vma 1 + sT 0.7071 Vds Vds
B Q
Vmb G *
C 0
Vmc 1 + sT 0.7071 Vqs Vqs
*
Ist 3.81 3 2 1 G *
A D
Ia 1 + sT 0.7071 Ids Ids
B Q
Ib G *
C 0
Ic 1 + sT 0.7071 Iqs Iqs
* G
Vdl 0.020454 1 + sT Vdcact Vdcpu
Vmpu Vds
Vmpu idref Ud
F B
- P P +
D + Eds
+ +
Ids_ref D - D + Eds
Vqref I I
F F
Ids
Ref Control *
Vqref Vdref Iqs 0.14
2 2
D A
Va_ref
Q B
Vb_ref
0.0 0 C
Vqs Vc_ref
0 0
1 1 iqref Uq
B
P P
+
+ - +
D - Iqs_ref D + D - Eqs Eqs
Vdref I I
F F F
Iqs
Vdcact *
Ids 0.14
Simulation Results without control:
Simulation Results with Direct control: