Verilog

A
Hardware Description Language
(HDL)

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 Motivation

Schematics can be cumbersome

32-bit busses & ripping out signals
Schematics are static
Little or no parameterization possible
Text-based input for HDLs
More like software development
Compilation to gates
Programmatic generation of HDL code from
higher level tools

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 Verilog

An HDL
Originated in industry
Later standardized by IEEE
C-like (not C, but C-like)

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 Styles of Coding in Verilog

Structural
1-to-1 correspondence with finished circuit
Manually instance circuit modules:

and(q, a, b);
fullAdd FA0(a, b, cin, cout, s);

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 Styles of Coding in Verilog

Dataflow
C-like expression syntax for combinational
logic functions:

assign cout = (a&b) | (a&cin) | (b&cin);

assign q = sel?b:a;

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 Styles of Coding in Verilog

Behavioral
What the circuit is to do rather than how it is
to do it
always @(posedge clk)
q <= d;

always @(posedge clk)

cnt <= cnt + 1;

A synthesis CAD tool will determine how to

implement that behavior

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Structural Verilog Design

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 Structural Verilog Design

module mux21(q, sel, a, b); selbar

input sel, a, b;
output q;
wire selbar, a1, a2; a a1
sel q
not(selbar, sel);
and(a1, selbar, a); a2
and(a2, sel, b); b
or(q, a1, a2);
endmodule

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 Structural Verilog Design

module mux21(q, sel, a, b);

input sel, a, b;
output q; Each module definition starts
wire selbar, a1, a2; with the keyword module and
ends with the keyword endmodule
not(selbar, sel);
and(a1, selbar, a); All details of the circuit fall
and(a2, sel, b); somewhere in between.
or(q, a1, a2);
endmodule

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 Structural Verilog Design

module mux21(q, sel, a, b);

input sel, a, b;
output q; The name of the module is specified
wire selbar, a1, a2; after the module keyword.

not(selbar, sel);
and(a1, selbar, a); Verilog is case-sensitive
and(a2, sel, b);
or(q, a1, a2); mux21 is a different module
endmodule name than MUX21

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 Structural Verilog Design

module mux21(q, sel, a, b);

The ports of the module
input sel, a, b;
are specified after the module
output q;
name. Each port must be
wire selbar, a1, a2;
declared in this port list.
not(selbar, sel);
In this case, there are
and(a1, selbar, a);
four ports to the module:
and(a2, sel, b);
or(q, a1, a2); q, sel, a, b
endmodule

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 Structural Verilog Design

module mux21(q, sel, a, b);

The direction of each port
input sel, a, b;
is declared using the
output q;
input and output statements.
wire selbar, a1, a2;
For this module, there are
not(selbar, sel);
three input ports (sel, a, b)
and(a1, selbar, a);
and one output port (q).
and(a2, sel, b);
or(q, a1, a2);
endmodule

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 Structural Verilog Design

module mux21(q, sel, a, b);

Internal wires that connect
input sel, a, b;
logic gates are declared.
output q;
wire selbar, a1, a2;
There are three internal wires
declared for this module:
not(selbar, sel);
and(a1, selbar, a);
selbar sel inverted
and(a2, sel, b);
a1 - output of first AND gate
or(q, a1, a2);
a2 - output of second AND gate
endmodule

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 Structural Verilog Design

Internal gates are instantiated using

one of several predefined built-in
module mux21(q, sel, a, b); gates.
input sel, a, b;
output q; The declaration for built-in gates is:
wire selbar, a1, a2;
type(output, in1, in2, );
not(selbar, sel);
and(a1, selbar, a); Built-in gates can take any number
and(a2, sel, b); of inputs (except not). Built-in
or(q, a1, a2); gates include:
endmodule
and(out, in1, in2, );
or(out, in1, in2, );
xor(out, in1, in2, );
not(out, in);
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 Structural Verilog Design

module mux21(q, sel, a, b); selbar

input sel, a, b;
output q;
wire selbar, a1, a2; a a1
sel q
not(selbar, sel);
and(a1, selbar, a); a2
and(a2, sel, b); b
or(q, a1, a2);
endmodule

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 Other Verilog Issues

Each statement ends with a semicolon (;)

Except the endmodule statement

Comments can be added using C comment style

// A pair of slashes for a single-line comment
/* Multiline comments also */

Verilog files are saved in a .v file (i.e. mux21.v)

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 Hierarchical Verilog Design
module mux41(q, sel, a, b, c, d); a b c d
input[1:0] sel;
input a, b, c, d;
output q;
wire tmp1, tmp2; 2
sel mux41
mux21 M0(tmp1, sel[0], a, b);
mux21 M1(tmp2, sel[0], c, d);
mux21 M2(q, sel[1], tmp1, tmp2);
endmodule a b q
c d

sel[0]
mux21 mux21

tmp1 tmp2
sel[1] mux21

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 Hierarchical Verilog Design
module mux41(q, sel, a, b, c, d);
input[1:0] sel; Multiple-bit wires can be
input a, b, c, d; declared and used. sel is
output q; a 2-bit wire.
wire tmp1, tmp2;

mux21 M0(tmp1, sel[0], a, b);

mux21 M1(tmp2, sel[0], c, d);
mux21 M2(q, sel[1], tmp1, tmp2); Individual bits of a multi-bit
endmodule wire can be accessed using
C-like array subscript
notation.
Most significant bit of sel

Least significant bit of sel

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 Hierarchical Verilog Design
module mux41(q, sel, a, b, c, d);
input[1:0] sel; Previously defined instance
input a, b, c, d; mux21 can be used within
output q; this module.
wire tmp1, tmp2;

mux21 M0(tmp1, sel[0], a, b);

mux21 M1(tmp2, sel[0], c, d);
mux21 M2(q, sel[1], tmp1, tmp2);
endmodule

module name instance name (each instance

name must be unique)

General instance format:

moduleName instanceName(port1, port2, portn);

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 More on Instances

Each instance must have an instance name

Except for built-in gates
Alternate syntax
Specify port name and wire
So you dont have to remember order

mux21 M1(.sel(sel[0]), .b(c), .a(d), .q(tmp2));

port name wire name

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 Constants

Often need to specify constant value

fullAdd FA0(a[0], b[0], 1b0, s[0], c[0]);

Wire a 1-bit 0 value to the carry-in of this full adder

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 More on Constants

1b0 A 1-bit number whose value is binary 0

3b110 A 3-bit number whose value is binary 110

4b00 An error

8d13 An 8-bit number whose value is decimal 13

24h00FFD2 A 24-bit number whose value is hex 00FFD2

General form: #bits base Value

(But without the spaces)

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 More on Multi-Bit Wires

input[7:0] x; // An 8-bit input wire

... x[0] ... // The LSB of x
... x[7] ... // The MSB of x
... x[2:0]... /* 3 LSBs of x */

Notice that C-style comments are allowed

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 More on Multi-Bit Wires

Take for example the add instruction from the LC-3

Instruction Register (IR)

ADD 0001 DR SR1 0 00 SR2 DR = SR1 + SR2

Opcode = IR[15:12]
DR = IR[11:9]

SR1 = IR[8:6] SR2 = IR[2:0]

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 More on Module Definitions
module mux21(q, sel, a, b);
input sel, a, b;
output q;
Declaring internal wires is
wire selbar; optional.

not(selbar, sel); WARNING: this means that

mis-spelled wire names may not
and(a1, selbar, a);
be caught by the Verilog
and(p2, sel, b); compiler !!!
or(q, a1, a2);
endmodule The code to the left doesnt
give a compile error. Finding
the error is a bit challenging.

Can you find it?

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 Instancing Modules

Built-in logic functions

and, or, not, xor
Independent of the technology used
Cells you have already designed
Like mux21 in previous slides
Require an instance name

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 More on Naming

Instance names can clash with signal names:

someCell a2(a2, sel, b); // Bad: the a2s clash

A Good Convention:
Signal names always start with lower case
letter
Instance names are always all uppercase
Remember, Verilog is case-sensitive

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 Module Instantiation Semantics

A Verilog design is not a program executed

one line at a time

It is a set of circuit modules that execute

concurrently
not(selbar, sel);
and(a1, selbar, a);
and(a2, sel, b);
or(q, a1, a2);

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 Verilog CAD Tool Flow

synthesize
mux21.v netlist.edn

physically
compile Implement

simulator completed
circuit

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