Analog and Digital Electronics

~ SJBIT
Analog and Digital Electronics

[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2015 -2016)
SEMESTER - III
Subject Code 15CS32 IA Marks 20
Number of Lecture Hours/Week 04 Exam Marks 80
Total Number of Lecture Hours 50 Exam Hours 03
CREDITS 04
Course objectives: This course will enable students to
Recall and Recognize construction and characteristics of JFETs and MOSFETs and differentiate with
BJT
Demonstrate and Analyze Operational Amplifier circuits and their applications
Describe, Illustrate and Analyze Combinational Logic circuits, Simplification of Algebraic Equations
using Karnaugh Maps and Quine McClusky Techniques.
Describe and Design Decoders, Encoders, Digital multiplexers, Adders and Subtractors, Binary
comparators, Latches and Master-Slave Flip-Flops.
Describe, Design and Analyze Synchronous and Asynchronous Sequential
Explain and design registers and Counters, A/D and D/A converters.
Module -1 Teaching
Hours
Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences

between JFETs and MOSFETs, Biasing MOSFETs, FET Applications, CMOS Devices.
Wave-Shaping Circuits: Integrated Circuit(IC) Multivibrators. Introduction to 10 Hours
Operational Amplifier: Ideal v/s practical Opamp, Performance Parameters, Operational
Amplifier Application Circuits:Peak Detector Circuit, Comparator, Active Filters, Non-
Linear Amplifier, Relaxation Oscillator, Current-To-Voltage Converter, Voltage-To-
Current Converter.
Text book 1:- Ch 5: 5.2, 5.3, 5.5, 5.8, 5.9, 5.1.Ch13: 13.10.Ch 16: 16.3, 16.4. Ch 17:
7.12, 17.14, 17.15, 17.18, 17.19, 17.20, 17.21.
Module -2
The Basic Gates: Review of Basic Logic gates, Positive and Negative Logic, Introduction
to HDL. Combinational Logic Circuits: Sum-of-Products Method, Truth Table to
10 Hours
Karnaugh Map, Pairs Quads, and Octets, Karnaugh Simplifications, Dont-care Conditions,
Product-of-sums Method, Product-of-sums simplifications, Simplification by Quine-
McClusky Method, Hazards and Hazard covers, HDL Implementation Models.
Text book 2:- Ch 2: 2.4, 2.5. Ch3: 3.2 to 3.11.
Module 3
1|Page
Data-Processing Circuits: Multiplexers, Demultiplexers, 1-of-16 Decoder, BCD to
Decimal Decoders, Seven Segment Decoders, Encoders, Exclusive-OR Gates, Parity
10 Hours
Generators and Checkers, Magnitude Comparator, Programmable Array Logic,
Programmable Logic Arrays, HDL Implementation of Data Processing Circuits. Arithmetic
Building Blocks, Arithmetic Logic Unit Flip- Flops: RS Flip-Flops, Gated Flip-Flops,
Edge-triggered RS FLIP-FLOP, Edge-triggered D FLIP-FLOPs, Edge-triggered JK FLIP-
FLOPs.
Text book 2:- Ch 4:- 4.1 to 4.9, 4.11, 4.12, 4.14.Ch 6:-6.7, 6.10.Ch 8:- 8.1 to 8.5.
Module-4
Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce

Circuits, Various Representation of FLIP-FLOPs, HDL Implementation of FLIP-FLOP.
Registers: Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In - 10 Hours
Serial Out, Parallel In - Parallel Out, Universal Shift Register, Applications of Shift
Registers, Register implementation in HDL. Counters: Asynchronous Counters, Decoding
Gates, Synchronous Counters, Changing the Counter Modulus.
(Text book 2:- Ch 8: 8.6, 8.8, 8.9, 8.10, 8.13. Ch 9: 9.1 to 9.8. Ch 10: 10.1 to 10.4
Module-5
Counters: Decade Counters, Presettable Counters, Counter Design as a Synthesis problem,

A Digital Clock, Counter Design using HDL. D/A Conversion and A/D Conversion:
10 Hours
Variable, Resistor Networks, Binary Ladders, D/A Converters, D/A Accuracy and
Resolution, A/D Converter-Simultaneous Conversion, A/D Converter-Counter Method,
Continuous A/D Conversion, A/D Techniques, Dual-slope A/D Conversion, A/D Accuracy
and Resolution.
Text book 2:- Ch 10: 10.5 to 10.9. Ch 12: 12.1 to 12.10.
Course outcomes:
After Studying this course, students will be able to
Acquire knowledge of
o JFETs and MOSFETs , Operational Amplifier circuits and their applications.
o Combinational Logic, Simplification Techniques using Karnaugh Maps, Quine McClusky
technique.
o Operation of Decoders, Encoders, Multiplexers, Adders and Subtractors.
o Working of Latches, Flip-Flops, Designing Registers, Counters, A/D and D/A Converters.
Analyze the performance of
o JFETs and MOSFETs , Operational Amplifier circuits
o Simplification Techniques using Karnaugh Maps, Quine McClusky Technique.
o Synchronous and Asynchronous Sequential Circuits.
Apply the knowledge gained in the design of Counters, Registers and A/D & D/A converters
Graduate Attributes (as per NBA)

1. Engineering Knowledge
2. Design/Development of Solutions(partly)
3. Modern Tool Usage
4. Problem Analysis
2|Page
Question paper pattern:
The question paper will have ten questions.
There will be 2 questions from each module.
Each question will have questions covering all the topics under a module.
The students will have to answer 5 full questions, selecting one full question from each module.
Text Books:
1. Anil K Maini, Varsha Agarwal: Electronic Devices and Circuits, Wiley, 2012.
2. Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 8th
Edition, Tata McGraw Hill, 2015
Reference Books:
1. Stephen Brown, Zvonko Vranesic: Fundamentals of Digital Logic Design with VHDL, 2nd Edition, Tata
McGraw Hill, 2005.
2. R D Sudhaker Samuel: Illustrative Approach to Logic Design, Sanguine-Pearson, 2010.
3. M Morris Mano: Digital Logic and Computer Design, 10th Edition, Pearson, 2008.
3|Page
Analog and Digital Electronics 15CS32
VTU Question Paper Solution
Module 1
Field Effect Transistors
1. Find the values of resistors Rb, Rc, Re and the transistor gain , for the
circuit. Ib=40A, Ic=4mA, Ve=2V, Vce=12V, Vcc=15V. Assume that the
transistor used in the circuit is a silicon transistor.(10 marks) (July 2016)
2. Find the values of resistance RB, RC, RE and transistor gain , for the
circuit shown in Fig. Q1.c Given that IB = 40 A, IC = 4mA, VE = 2V,
VCE = 12V and supply voltage VCC = 15V. Assume the transistor used in
circuit is a silicon transistor. (4 marks) (Dec 2015)
Dept. of CSE, SJBIT Page 1

Logic Design 15CS32
3. Determine the value of the resistors Re and Rc for the circuit shown in
figure given that R1=5K , R2=1K , =200, Vceq=5v and Iceq=2mA for the
silicon made transistor. (8 marks) (Dec 2014)
Applying KVL to Collector Emitter loop,

Vcc-IcRc-Vce-IeRe = 0 as Ie~=Ic,
12 - 2e-3*(Rc+Re) 5 = 0
Rc + Re = 3.5Kohm
Consider Approx. method as I1> Ib

Vb= VccR2 / R1+R2 = 2V.
Ve = Vb Vbe
Re = 0.65Kohm and Rc = 2.85Kohm
4. Explain the working of a N-channel E-MOSFET with neat diagram. Explain

with a Diagram output characteristics of the same.(10 Marks)(June 2014)

The graphic symbols for the n-channel and p-channel JFETs are provided in Fig.
Note that the arrow is pointing in for the n-channel device of Fig to represent the
direction in which IG would flow if the p-n junction were forward-biased. The
level of VGS that results in ID _ 0 mA is defined by VGS _ VP, with VP being a
negative voltage for n-channel devices and a positive voltage forp-channel
JFETs.On most specification sheets the pinch-off voltage is specified as
VGS(off) rather than VP. A specification sheet will be reviewed later in the
chapter when the primary elements of concern have been introduced.

Logic Design 15CS32
5. Explain the working of a CMOS inverter.(10 Marks) (June 2015)

Complementary MOSFET (CMOS) technology is widely used today to form circuits in
numerous and varied applications. Todays computers CPUs and cell phones make
use of CMOS due to several key advantages. CMOS offers low power dissipation,
relatively high speed, high noCSE margins in both states, and will operate over a wide
range of source and input voltages (provided the source voltage is fixed). Next I will
attempt to explain just how this logic gate works now that you have some idea of
how important CMOS is in your day-to-day life.
A CMOS circuit is composed of two MOSFETs. The top FET (MP) is a PMOS type
device while the bottom FET (MN) is an NMOS type. The body effect is not present in
either device since the body of each device is directly connected to the devices
source. Both gates are connected to the input line. The output line connects to the
drains of both FETs.
6. Explain the construction & working and principle of operation of an n-channel

JFET. (10 Marks)(Dec 2015)
JFETs are of two types, namely N-channel JFETs and P-channel JFETs. Generally N-
channel JFETs are more preferred than P-channel. N-channel and P-channel JFETs are
shown in the figures below. The structure is quite simple. In an N-channel JFET an N-
type silicon bar, referred to as the channel, has two smaller pieces of P-type silicon
material diffused on the opposite sides of its middle part, forming P-N junctions, as
illustrated in figure. The two P-N junctions forming diodes or gates are connected

internally and a common terminal, called the gate terminal, is brought out. Ohmic
contacts (direct electrical connections) are made at the two ends of the channelone
lead is called the Source terminal S and the other Drain terminal D.
The silicon bar behaves like a resistor between its two terminals D and S. The gate
terminal is analogous to the base of an ordinary transistor (BJT). It is used to control
the flow of current from source to drain. Thus, source and drain terminals are
analogous to emitter and collector terminals respectively of a BJT. In the figure below,
the gate is P-region, while the source and the drain are N-regions. Because of this, a
JFET is similar to two diodes. The gate and the source form one of the diodes, and the
drain form the other diode. These two diodes are usually referred as the gate-source
diode and the gate-drain diode. Since JFET is a silicon device, it takes only 0.7 volts
for forward bias to get significant current in either diode.
Figure: JFET construction
7. Explain the small signal operation of amplifiers. (10 Marks)(June 2015)

When the voltage increases to its positive peak, the instantaneous operating point
moves from Q to the upper point as shown, on the other hand when the sine wave
decreases to its negative peak the instantaneous operating point moves from Q to lower
point. Large AC base voltage produces large variations whereas small as base voltage
produces small variations. The AC emitter current is not a perfect replica of the AC
base voltage because of the curvature of the graph. Since the graph is curved upward,

Logic Design 15CS32
the positive half cycle of AC emitter current is elongated and the negative half cycle is
compressed, this stretching and compressing of alternate half cycles is called
distortion. One way to reduce distortion is by keeping the AC base voltage small, when
the signal is small, the changes in ac emitter current are almost directly proportional to
the changes in AC base voltage
8. What are the differences between JFET & MOSFET. (2 Marks)(Dec 2015)
MOSFET: It can be operated in both depletion & enhancement mode. E MOSFET are
operated only in enhancement mode. Input resistance is high of order tera ohms, It has
low drain resistance, leakage current is small of nano amperes and easier to construct,
whereas for an JFET: It operates in depletion mode only, Input resistance is low of
giga ohms, has high drain resistance of 100Kohms, leakage current is high of micro
amperes and difficult in construction.
9. Explain with neat sketches the operation and characteristics of N-channel DE-
MOSFET(8 Marks) (Dec 2014)
Figure shows the construction of N-channel depletion MOSFET. It consists of a highly
doped P-type substrate into which two blocks of heavily doped N-type material are
diffused forming the source and drain. An N-channel is formed by diffusion between
the source and drain. The type of impurity for the channel is the same as for the source
and drain. Now a thin layer of SiO2 dielectric is grown over the entire surface and
holes are cut through the SiO2 (silicon-dioxide) layer to make contact with the N-type
blocks (Source and Drain). Metal is deposited through the holes to provide drain and
source terminals, and on the surface area between drain and source, a metal plate is
deposited. This layer constitutes the gate. Si02 layer results in an extremely high input
impedance of the order of 1010 to 1015 Q for this area. The chip area of a MOSFET is
typically 0.003 um2 or less which is about only 5% of the area required by a BJT. A P-
channel DE-MOSFET is constructed like an N-channel DE-MOSFET, starting with an
N-type substrate and diffusing P-type drain and source blocks and connecting them
internally by a P-doped channel region. The working principle of MOSFET depends
up on the MOS capacitor. The MOS capacitor is the main part. The semiconductor
surface at below the oxide layer and between the drain and source terminal can be
inverted from p-type to n-type by applying a positive or negative gate voltages
respectively.

Figure: Operation of D-MOSFET Figure: Construction of D-MOSFET
10. Explain with neat diagram: i) Peak detector circuit ii) Absolute value circuit
and their working.(10 Marks)(July 2015)
Peak Detector Circuit

Logic Design 15CS32
Peak detector circuit produces a voltage at the output equal to peak amplitude
(positive or negative) of the input signal. It is a clipper circuit with a parallel resistor-
capacitor connected at its output. The clipper here reproduces the positive half cycles.
During this period, the diode D1 is forward-biased. The capacitor rapidly charges to the
positive peak from the output of the opamp.

Input / Output Waveform of Peak Detector Circuit
Absolute Value Circuit

It is the configuration of opamp that produces at itsV.output
Also, Vax isvoltage
related to Vo by
equal toVthe
x =
absolute
opamp, we
value of the input voltage. The circuit shown above is the dual half wave
rectifier
can circuit. When the applied input is of positive polarity (+V), diode D1 is
forward biased and diode D2 is reverse biased. The output (Vo) in thiscase is equal to
+V. When the applied input is of negative polarity (-V), diode D1 is reverse biased and
diode D2 is forward biased. By applying Kirchoffs Current Law (KCL) at the
inverting terminal of the determine voltage (Vx) to be equal toimplies that Vo = V.
Thus the output always equals the absolute value of the input signal.
Module-2
The Basic gates
1. What are Universal gates? Implement the basic gates using Universal gates only.
(June / July 16) 8 Marks
,A universal gate is a gate which can implement any Boolean function without need to use any other
gate type. The NAND and NOR gates are universal gates
Implementing an Inverter Using only NAND Gate
The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).
1. All NAND input pins connect to the input signal A gives an output A.

Logic Design 15CS32
2. One NAND input pin is connected to the input signal A while all other input pins are connected
to logic 1. The output will be A.
Implementing AND Using only NAND Gates
An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a
NAND gate with its output complemented by a NAND gate inverter).
Implementing OR Using only NAND Gates
An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a
NAND gate with all its inputs complemented by NAND gate inverters).
Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT functions.
NAND Gate is a Universal Gate:
To prove that any Boolean function can be implemented using only NOR gates, we will show that
the AND, OR, and NOT operations can be performed using only these gates.
Implementing an Inverter Using only NOR Gate
The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

Implementing OR Using only NOR Gates
An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate
with its output complemented by a NOR gate inverter)
Implementing AND Using only NOR Gates
An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a
NOR gate with all its inputs complemented by NOR gate inverters)
2 .Using Karnaugh Map,simplify the following boolean expression and give the
implementation of the same using i)NAND gates only(SOP) ii) NOR gates only (POS )
F(w,x,y,z)=m(0,1,2,4,5,12,14)+dc(8,10) (June/ July 16) 8 Marks
a. NAND Gate (SOP form)
CD CD CD CD
AB 1 1 1

Logic Design 15CS32
AB 1 1
AB 1 1
AB X X
F(A,B,C,D) = CD + AC + AD + BD
b. NOR gate (POS form)

F(A,B,C,D) = (A + C)(C+D)(A+D)(B+D)
3.Explain Duality Theorem? (June/ July 16) 4 Marks

One can transform the given expression by interchanging the operation (+) and ()
as well as the identity elements 0 and 1 . Then the expression will be referred as
dual of each other. This is known as the principle of duality. Example x + x = 1
then the dual expression is x x =0
4 .Define: i) Rise time ii) Fall time iii) Period and iv) Frequency.
(July 15), (Dec 15) (8 Marks)
i) A rising edge is the transition from low to high. It is also named positive edge. When
a circuit is rising edge-triggered, it becomes active when its clock signal goes from
low to high, and ignores the high-to-low transition.
ii) A falling edge is the high to low transition. It is also known as the negative edge.
iii) For each dot, "f" is the frequency in hertz (Hz) meaning the number of times per
second (i.e. cycles per second) that it flashes while "T" is the flashes'
iv) period in seconds (s), meaning the number of seconds per cycle. Each T and f are
reciprocal.
5.What is an universal gate? List the Universal gates and prove their universalities.
(July 15) (6 Marks)
Universal Gates are : NAND ,NOR

6.Write the verilog code for given expression. Y=AB+CD (July 15) (6Marks)
// Verilog code for AND-OR-INVERT gate module
AOI (input A, B, C, D, output F);
/* start of a block comment
wire F; wire AB,
CD, O; assign AB =
A & B; assign CD
= C & D; assign O =
AB | CD; assign F
= ~O;
end of a block comment */
// Equivalent...
wire AB = A & B;
wire CD = C & D;
wire O = AB | CD;
wire F = ~O; endmodule
// end of Verilog code
7.Using Karnaugh Map,simplify the following boolean expression and give the
implementation of the same using i)NAND gates only(SOP) ii) NOR gates only
(POS )
a.F(w,x,y,z)=m(0,1,2,4,5,12,14)+dc(8,10) (Dec 14 / Jan 15) 10 Marks
NAND Gate (SOP form)

Logic Design 15CS32
CD CD CD CD
AB 1 1 1
AB 1 1
AB 1 1
AB X X
F(A,B,C,D) = CD + AC + AD + BD
a.NOR gate (POS form)

F(A,B,C,D) = (A + C)(C+D)(A+D)(B+D)
8.Mention the Universal gates? Implement with respect to the basic gates.
(Dec 14 / Jan 15) 10 Marks Universal Gates are : NAND ,NOR
9.Define Logic. Explain different types of logic. ( July 14) 10 Marks
Positive Logic: With reference to positive logic, logical 1 state is the most positive logic
or voltage level and logic 0 state is the most negative logic or voltage level. In other
words, active high level is 1 and active low level is 0. For instance, V(0) = 0V and V(1) =
5V, V(0) = 5V and V(1) = 15V.

Negative Logic: With reference to negative logic, logic 0 state is the most positive logic
or voltage level and logic 1 state is the most positive logic or voltage level. In other
words, active high level is 0 and active low level is 1. For instance, V(0) = 5V and V(1) =
0V, V(0) = 15V and V(1) = 5V.
10.Differentiate between Analog and Digital Signals. ( July 14) 10 Marks.
An Analog signal is any continuous signal for which the time varying feature (variable)
of the signal is a representation of some other time varying quantity, i.e., analogous to
another time varying signal. It differs from a digital signal in terms of small fluctuations
in the signal which are meaningful.
A digital signal uses discrete (discontinuous) values. By contrast, non-digital (or analog)
systems use a continuous range of values to represent information. Although digital
representations are discrete, the information represented can be either discrete, such as
numbers or letters, or continuous, such as sounds, images, and other measurements of
continuous systems.

Logic Design 15CS32
Comparison chart
Analog Digital
Analog technology records waveforms Converts analog waveforms into set

Technology:
as they are. of numbers and records them. The
numbers are converted into voltage
Analog Digital
stream for representation.
Uses continuous range of values to Uses discrete or discontinuous

Representation: represent information. values to represent information.
Can be used in various computing

Uses: platforms and under operating systems Computing and electronics
like Linux, Unix, Mac OS and Windows.
Analog signal is a continuous signal

Digital signals are discrete time
which transmits information as a
Signal: signals generated by digital
response to changes in physical
modulation.
phenomenon.
Analog clocks indicate time using Digital clocks use numeric

Clocks:
angles. representation to indicate time.
Computer: Analog computer uses changeable

Digital computers represent

continuous physical phenomena such as changing quantities incrementally
electrical, mechanical, hydraulic as and when their values change.
quantities so as to solve a problem.

Logic Design 10CS33
11.Using K-map find the reduced SOP form of f(A,B,C,D)=M(5,6,7,12,13)+d(4,9,14,15).

(July 15) (5 marks)
00 01 11 10
00 0 0 0 0
01
11 x 1 1 1
10 1 1 x x
ans: y=B
0 x 0 0
12.What is hazard? List the types of hazards and explain static_0 and static-1 hazards.
(July 15) (5 Marks)
Static 1 hazard
The delay in the gates, the output Z would be constant at 1.The spike is due to the gate delay and the
fact that not every path from on input to the output is the same length
The static 0
hazard is caused by two OR gates where one holds the output zero before the transition and the
other after the transition, and it is possible for them to both be 1 during the transition The fix is to
put in an extra OR gate to hold the output zero during the transition
13.Simplify the following using Mc-Cluskey method f=M(4,8,10,11,12,15)+d(9,14)

(July 15) (10 Marks)
This expression says that the output function f will be 1 for the minterms 4,8,10,11,12 and 15 (denoted
by the 'm' term). But it also says that we don't care about the output for 9 and 14 combinations
(denoted by the 'd' term). ('x' stands for don't care).
ABCDf
m0 0 0 0 0 0
m1 0 0 0 1 0
m2 0 0 1 0 0

Logic Design 10CS33
m3 0 0 1 1 0
m4 0 1 0 0 1
m5 0 1 0 1 0
m6 0 1 1 0 0
m7 0 1 1 1 0
m8 1 0 0 0 1
m9 1 0 0 1 x
m10 1 0 1 0 1
m11 1 0 1 1 1
m12 1 1 0 0 1
m13 1 1 0 1 0
m14 1 1 1 0 x
m15 1 1 1 1 1
One can easily form the canonical sum of products expression from this table, simply by summing
the minterms(leaving out don't-care terms) where the function evaluates to one:
which is not minimal. So to optimize, all minterms that evaluate to one are first placed in a minterm
table. Don't-care terms are also added into this table, so they can be combined with minterms:
Number of 1sMintermBinary Representation
m4 0100
1
m8 1000m9
1001

Logic Design 10CS33
2 m10 1010
m12 1100
m11 1011
3
m14 1110
4 m15 1111
At this point, one can start combining minterms with other minterms. If two terms vary by only a single
digit changing, that digit can be replaced with a dash indicating that the digit doesn't matter. Terms that
can't be combined any more are marked with a "*". When going from Size 2 to Size 4, treat '-' as a third
bit value. For instance, -110 and -100 or -11- can be combined, but 110 and 011- cannot. (Trick: Match
up the '-' first.)
Number of 1sMinterm0-CubeSize 2 Implicants Size 4 Implicants

m4 m8 0100 m(4,12) -100* m(8,9,10,11) 10--*
m(8,9) 100-
m(8,10,12,1
-- 1000 m(8,10) 10-0 4) 1--0*
m(8,12) 1-00
-- -- m(9,11) 10-1
m(10,11) 101- --
1 m9 m10 -- m(10,14) 1-10
--
-- 1001
m(10,11,14,15) 1-1-*
1010
--
--
--
2
m12 1100 m(12,14) 11-0 --
m11 1011 m(11,15) 1-11 --

3
m14 1110 m(14,15) 111- --
4 m15 1111 -- --
Note: In this example, none of the terms in the size 4 implicants table can be combined any further.
Be aware that this processing should be continued otherwise (size 8 etc.).

Logic Design 10CS33
Step 2: prime implicant chart
None of the terms can be combined any further than this, so at this point we construct an
essential prime implicant table. Along the side goes the prime implicants that have just been
generated, and along the top go the minterms specified earlier. The don't care terms are not
placed on top - they are omitted from this section because they are not necessary inputs.
4810111215=>ABCD
m(4,12)* X X =>-100
m(8,9,10,11) XXX =>10--
m(8,10,12,14) XX X
m(10,11,14,15)* XX X=>1-1-
To find the essential prime implicants, we run along the top row. We have to look for columns
with only 1 star. If a column has only 1 star, this means that the minterm can only be covered by
1 prime implicant. This prime implicant isessential. For example: in the first column, with
minterm 4, there is only 1 star. This means that m(4,12) is essential. So we place a star next to it.
Minterm 15 also only has 1 star. This means that m(10,11,14,15) is also essential. Now all
columns with 1 star are covered.
The second prime implicant can be 'covered' by the third and fourth, and the third prime
implicant can be 'covered' by the second and first, and neither is thus essential. If a prime
implicant is essential then, as would be expected, it is necessary to include it in the minimized

boolean equation. In some cases, the essential prime implicants do not cover all minterms, in
which case additional procedures for chart reduction can be employed. The simplest "additional
procedure" is trial and error, but a more systematic way is Petrick's Method. In the current
example, the essential prime implicants do not handle all of the minterms, so, in this case, one

Logic Design 10CS33
can combine the essential implicants with one of the two non-essential ones to yield one
equation:
Both of those final equations are functionally equivalent to the original, verbose equation:
14. Find the prime implicant with the help of Qunie-Mc Clusky Method.
F(W,X,Y,Z) = m(1,3,6,7,8,9,10,12,13,14) (Dec 14/Jan 15) ) (10 Marks)
No WXYZ Index
1 0001 1
3 0011 2
6 0110 2
7 0111 3
8 1000 1
9 1001 2
10 1010 2
12 1100 2
13 1101 3
14 1110 3
13 1101 3
14 1110 3
List the minterm in increasing order of their index
No WXYZ Index
1 0001 1
8 1000 1
3 0011 2
6 0110 2

Logic Design 10CS33
9 1001 2
10 1010 2
12 1100 2
7 0111 3
13 1101 3
14 1110 3
No WXYZ Index
1,3 00_1 2
1,9 _001 2
8,9 100_ 2
8, 10 10_0 2
8,12 1_00 2
3,7 0_11 3
6,7 011_ 3
6,14 _110 3
9,13 1_01 3
10,14 1_10 3
12,13 110_ 3
12,14 11_0 3
Prime Implicant: ABD + BCD + ACD + ABC + BCD + AC + AD
15.Does circuit in below figure experience hazard? If so, verify the same with timing diagram
Explain the significance of Demorgans theorem
(Dec 14 / Jan 15) 10 Marks

Logic Design 10CS33
16.What is a karnaugh map? State the limitations of karnaugh map.

(July 14) 10 Marks
A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is
made up of squares, with each squares representing one minterm of the function. Generally
it is limited to six variable map (i.e) more then six variable involving expression are not
reduced. ii) The map method is restricted in its capability since they are useful for
simplifying only Boolean expression represented in standard form.
17.Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (July 14) 10 Marks
ABC + ABC' + AB'C + A'BC
=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC =A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
18.Implement the following SOP function

F = XZ + YZ + XYZ Compare TTL and CMOS families and the integration
level of ICs (Dec 15) 10 Marks
The Comparison of TTL and CMOS is clearly illustrated in the following table as an example of
differences in the logic families:
TTL CMOS
Faster drive Low power consumption

Stronger
Simpler to make
capability
Greater packing density
Better noise immunity

Logic Design 10CS33
Integration Levels:
The devices greatly differ in the density of fabrication ie the levels of integration used.Depending
on the number of transistors/diodes/gates used in the chip they are broadly classified as :
SSI -small scale integration

MSI -medium scale integration
LSI -large scale integration
VLSI -very large scale integration
ULSI -ultra large scale integration
GSI -giant scale integration
Levels of Transistors/package Gates/chip Applications

integration
SSI 1-100 <12 Logic gates Op-amps
MSI 100-1000 12-99 Registers Filters
LSI 1000-10000 1000 8 bit processor, A/D converter

Logic Design 10CS33
VLSI 10k gates/chip 16,32 bit processor
256KB memory
DS processor
ULSI 100k gates/chip 64 bit processor
8 MB memory
Image processor
GSI 1M gates/chip 64 MB memory

multiprocessor
19.Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC. (Dec 15) 10 Marks
ABC + ABC' + AB'C + A'BC
=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC =A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
20.Find the prime implicant with the help of Qunie-Mc Clusky Method.
F(W,X,Y,Z) = m(1,3,6,7,8,9,10,12,13,14) (July 16) 10 Marks
Step 1: Represent each minter in its 1-0 notation

Logic Design 10CS33
no. minterm 1-0 notation index
0 wxyzwx 0000 0
yzw
2 xyz 0010 1
wxy
3 0011 2
zwx
4 yzw 0100 1
xyz
8 wxy 1000 1
zwx
10 yzw 1010 2
xyz
12 1100 2
13 1101 3
14 1110 3
Step 2: List the minterm in increasing order of their index.

No. wxyz index
0 0000 Index 0
2 0010
4 0100 Index 1
8 1000
3 0011
10 1010 Index 2
12 1100
13 1101
14 1110 Index 3

Logic Design 10CS33
Wxyz index
0.2 000
0,4 000
0,8 - 000
001
2,3
- 010
2,10
- 100
4,12 100
8,10 100
8,12 110
10,14 110
12,13 11-0
12,14
wxyz
(0, 2, 8, 10) __ 0 __ 0
(0, 4, 8,12 ) __ __ 0 0(index 0)
(8,10,12,14) 1__ __ 0 (index 1)
F(w,x,y,z)=x z + y z +w z+w x y +w x z
PRIME IMPLICANTS AND IRREDUNDANT EXPRESSION
F(W,X,Y,Z)= M(0,1,2,5,7,8,9,10,13,15)
A=X Y , B= X Z C= Y Z D= X Z
P = (A+B)(A+C) (B)(C+D)(D)(A+B)(A+C)(B)(C+D)(D)
P = (A +C)(BD) = ABD +BCD

Logic Design 10CS33
F1(W,X,Y,Z)= ABD =X Y +X Z +X Z
F2(W,X,Y,Z) = BCD = X Z + Y Z +X Z
21.Define impliant. Explain prime and essential prime implicants with example.
(July 16)10 Marks
In Boolean logic, an implicant is a "covering" (sum term or product term) of one or more
minterms in a sum of products (or maxterms in a product of sums) of a boolean function.
Formally, a product termP in a sum of products is an implicant of the Boolean functionF if
PimpliesF. More precisely:
P implies F (and thus is an implicant of F) if F also takes the value 1 whenever P equals
1.
where xF is a Boolean function of n
variables.
xP is a product term.
A prime implicant of a function is an implicant that cannot be covered by a more
general (more reduced - meaning with fewer literals) implicant. W.V. Quine defined a
prime implicant of F to be an implicant that is minimal - that is, the removal of any
literal from P results in a non-implicant for F.
Essential prime implicants are prime implicants that cover an output of the function
that no combination of other prime implicants is able to cover.
Using the example above, one can easily see that while (and others) is a prime
implicant, are not. From the latter, multiple literals can be removed to
make it prime: x, and can be removed, yielding . xAlternatively, and can be
removed, yielding .
x Finally, and can be removed, yielding .

Logic Design 10CS33
Module-3
Data-Processing Circuits
1.Implement the following function using a 8:1 multiplexer:

f(a,b,c,)= M(0,1,3,4). (July 15) (10 Marks)
2.Realize the following function using the 3:8 decoder .F1(A,B,C) = m(1,2,4,5), F2(A,B,C)
= m(1,5,7) (July 15) (6 Marks)

Logic Design 10CS33
3. What is a magnitude comparator? Explain with a neat block diagram an n-bit

magnitude comparator (July 15) 4marks.
A magnitude comparator is a combinational circuit that compares
Two numbers, A and B, and then determines their relative magnitudes.

A>B
A = B
A <B
To determine if A is greater than or less than B, we inspect the relative magnitudes of
significant digits.
If the two digits are equal, we compare the next lower significant pair of digits. The
comparison continues until a pair of unequal digits is reached

Logic Design 10CS33
4.Implement 4:1 mux using 2:1 mux (Dec 14 /Jan 15) 10 Marks
5.What is a Multiplexer. Design a 4:1 multiplexer using gate. (Dec 14 /Jan 15) 10
Marks
A multiplexer (or MUX) is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n
select lines, which are used to select which input line to send to the output.Multiplexers are
mainly used to increase the amount of data that can be sent over the network within a
certain amount of time and bandwidth. A multiplexer is also called a data selector. They
are used in CCTV, and almost every business that has CCTV fitted, will own one of these.

Logic Design 10CS33
6.Explain the 8 word X 4 bit ROM with the help of block diagram. (July 14) 8 Marks

Logic Design 10CS33
7.Explain the Implementation of Full adder using PLA (July 14) 6 Marks
SUM = XYCin + XYCin+ XYCin + XYCin
Carry = XCin +YCin + XY
8.Differentiate between PROM, PAL, PLA (July 14) 8 Marks

in the AND-OR arrays. Figure shows the locations of the programmable connections for the
three types.

Logic Design 10CS33
9.Show that using a 3-to-8 decoder and multi input OR gate. The following Boolean
expression can be realized.F1(A,B,C) = m(1,2,4,5), F2(A,B,C) = m(1,5,7)
(Dec15 ) 10 Marks

Logic Design 10CS33
10.Implementation of F(A,B,C,D)= (m(1,3,5,7,8,10,12,13,14), d(4,6,15)) By using a 16to-1

multiplexer. (Dec15 ) 10 Marks
11.Implement 4:16 decoder using 2:4 decoders

(July 16) 6 Marks.

Logic Design 10CS33
12. Explain n bit magnitude comparator (July 16) 8 Marks.
A magnitude comparator is a combinational circuit that compares Two

numbers, A and B, and then determines their relative magnitudes.
A>B
A = B
A <B
To determine if A is greater than or less than B, we inspect the relative magnitudes of
significant digits.
If the two digits are equal, we compare the next lower significant pair of digits. The
comparison continues until a pair of unequal digits is reached

Logic Design 10CS33
13.Design 7 segment decoder using PLA (July 16) 6 Marks
14. With a neat block diagram, explain the working of a Master-Slave Jk flip flop. Also
write its truth table. (July 15) (10 Marks)
All sequential circuits that we have seen in the last few pages have a problem (All level
sensitive sequential circuits have this problem). Before the enable input changes state
from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes,
then another state transition occurs for the same enable pulse. This sort of multiple
transition problem is called racing.
If we make the sequential element sensitive to edges, instead of levels, we can overcome
this problem, as input is evaluated only during enable/clock edges.

Logic Design 10CS33
In the figure above there are two latches, the first latch on the left is called master latch
and the one on the right is called slave latch. Master latch is positively clocked and slave
latch is negatively clocked.
15. Define: i)Flip flop ii) Hold time iii) Set up time iv)Characteristic
equation.
i) Flip Flop: is an bistable electronic circuit which has two states

on and off.
ii) Hold time is defined as the minimum amount of time after the
clock's active edge during which data must be stable.
iii) Set up time = the time passed between the completion of the
last product of the old series and the completion of the first
good product of the new series. During the set up actions are
made in relation to: the change of tools,
iv) Character equation:

Logic Design 10CS33
16.Show how SR flip flop can be converted to a JK flip flop. (Dec 14 /Jan 15) 10 Marks
In SR FF, S=R=1 condition is not allowed.
JK FF is modified version of
SR FF.
Due to feedback from output
to input AND Gate J=K=1 is
toggle condition for JK FF.
The output is complement
of the previous output.
17.Write HDL design of D and JK Flip flop (Dec 14 /Jan 15) 10 Marks //D
flip-flop
module D_FF (Q,D,CLK);
Logic Design 10CS33
output Q;
input D,CLK;
reg Q;
always @(posedge CLK)
Q = D; endmodule module
JK_FF (J,K,CLK,Q,Qnot);
output Q,Qnot; input J,K,CLK;
reg Q; assign Qnot = ~ Q ;
always @(posedge CLK)
case({J,K}) 2'b00: Q = Q;
2'b01: Q = 1'b0;
2'b10: Q = 1'b1;
2'b11: Q = ~ Q;
endcase endmodule
18.With the help of neatdiagram explain the working of a Master Slave JK flip flop
(July 14) 10 Marks
this problem, as
input is evaluated
only during enable/clock
edges.
In the figure above there

are two latches, the first latch on the left is called master latch and the one on the right is
called slave latch. Master latch is positively clocked and slave latch is negatively clocked.

Logic Design 10CS33
19.What do you mean by characteristic equation of a flip-flop? Derive characteristic

equation for SR flip flop (July 14) 10 Marks
A descriptions of the next-state table of a flip-flop . Constructing from the Karnaugh map
for Qt+1 in terms of the present state and input.

Logic Design 10CS33
20.With the help of block diagram, explain the working of a JK Master-Slave flip flop.
(Dec15) 10 Marks
this problem, as input is evaluated only during enable/clock edges.
8.
In the figure above there are two latches, the first latch on the left is called master latch
and the one on the right is called slave latch. Master latch is positively clocked and slave
latch is negatively clocked.

Logic Design 10CS33
9.
21.Differentiate between combinational circuit and sequential circuit.

(Dec15) 10 Marks
Combinational Logic Circuit :
The circuit in which outputs depends on only present value of inputs. So it is possible to
describe each output as function of inputs by using Boolean expression. No memory
element involved. No clock input. Circuit is implemented by using logic gates. The
propagation delay depends on, delay of logic gates. Examples of combinational logic
circuits are : full adder, subtractor, decoder, codeconverter, multiplexers etc.
inputs Combinational
outputs
Logic Circuit
Sequential Circuits :

Logic Design 10CS33
Sequential Circuit is the logic circuit in which output depends on present value of inputs
at that instant and past history of circuit i.e. previous output. The past output is stored by
using memory device. The internal data stored in circuit is called as state. The clock is
required for synchronization. The delay depends on propagation delay of circuit and
clock frequency. The examples are flip-flops, registers, counters etc.
inputs outputs
Combinational
Logic Circuit
Memory Device
22..Explain Schmitt trigger (July 16) 6 Marks

The circuit is designed with a positive feedback and hence will have a regenerative action which
will make the output switch levels. Also, the use of positive voltage feedback instead of a
negative feedback, aids the feedback voltage to the input voltage, instead of opposing it. The use
of a regenerative circuit is to remove the difficulties in a zero-crossing detector circuit due to
low frequency signals and input noise voltages.

Logic Design 10CS33
23.Give transition diagram of JK and T Flip flops. (July 16) 8 Marks
24. Show how a D flip flop converted into JK flipflop (July 16) 6 Marks
D Flip Flop to JK Flip Flop
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is
expressed in terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the
conversion from D to JK are given in the figure below.

Logic Design 10CS33

Logic Design 10CS33
Module-4
Flip-Flops
1.Draw the logic diagram of a 4-bit serial in serial out shift register using J-K flip flop
and explain. (July 15) (8 Marks)
The serial in/serial out shift register accepts data serially--that is, one bit at a time on a single
line. It produces the stored information on its output also in serial form. With four stages, this
register can store up to four bits of data; its-storage capacity is four bits.
2.Explain briefly serial adder with a neat sketch. (July 15) (8 Marks)
3.Write a verilog code for switched tail counter. (July 15) (4 Marks)
Verilog code for Johnson counter.
module jc (clk,reset,q);
input clk,reset; output
[3:0] q; reg [3:0]q;
always @ (negedge clk,negedge reset) if
(~reset)
q=4b0000;
else begin

Logic Design 10CS33
q[0]<=~q[3];
q[1]<=q[0];
q[2]<= q[1];
q[3]<=q[2]; end
endmodule
4.Explain Johnson Counter with neat diagram and timing diagram
(Dec14 / Jan 15) 10 Marks
The switch-tail ring counter, also know as the Johnson counter, overcomes some of the
limitations of the ring counter. Like a ring counter a Johnson counter is a shift register fed back
on its' self. It requires half the stages of a comparable ring counter for a given division ratio. If
the complement output of a ring counter is fed back to the input instead of the true output, a
Johnson counter results. The difference between a ring counter and a Johnson counter is which
output of the last stage is fed back (Q or Q'). Carefully compare the feedback connection below
to the previous ring counter.

Logic Design 10CS33
5.Write verilog code for Shift Register. (Dec14 / Jan 15) 10 Marks
module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr); input s1,s0; //Select inputs input lfin,
rtin; //Serial inputs input CLK,Clr; //Clock and Clear input [3:0] Pin; //Parallel
input output [3:0] A; //Register output reg [3:0] A; always @ (posedge CLK or
negedge Clr) if (~Clr) A = 4'b0000; else case ({s1,s0})
2'b00: A = A; //No change
2'b01: A = {rtin,A[3:1]}; //Shift right
2'b10: A = {A[2:0],lfin}; //Shift left
//Parallel load input
2'b11: A = Pin;
endcase
endmodule
6.Give applications of J-K flip-flops. (July 14) 10 Marks
2. J-K flip-flops are used in shift registers.

3. J-K flip-flops are used in counters.
4. Data storage
5. Data transfer
6. Counter
7. Frequency division
7. Draw the general block diagram of multivibrator. (July 14 ) 10 Marks
F1 and F2 are the options for the connections of passive components according to the types of
multivibrator to design.
For example
(a) Astable Multivibrator: F1 = C1 and F2 = C2.
(b) Monostable Multivibrator: F1 = C and F2 = R.

Logic Design 10CS33
(c) Bistable Multivibrator : F1 = F2 = Parallel combination of R and C of different

values.
8.Explain a 4 bit universal shift register in detail and give its timing diagram.
(Dec15) 10 Marks
9.With neat timing diagram, explain the working of a 4-bit SISO register.

Logic Design 10CS33
(Dec15) 10 Marks
The serial in/serial out shift register accepts data serially--that is, one bit at a time on a single
line. It produces the stored information on its output also in serial form. With four stages, this
register can store up to four bits of data; its-storage capacity is four bits.
10.Design a 3 bit PISO(DFlip flop) (July 16)6 marks
Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PAto PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this system a clock pulse is not required to parallel load the register as it is already
present, but four clock pulses are required to unload the data.
4-bit Parallel-in to Serial-out Shift Register

Logic Design 10CS33
11. Design two 4 bit serial adder. (July 13) 6marks
12. Design a 4 bit Johnson counters with sate table. (July 16)8 marks
4-bit Ring Counter
Clock Pulse No FFA FFB FFC FFD
0 0 0 0 0
1 1 0 0 0

Logic Design 10CS33
Truth Table for a 4-bit

Johnson Ring 2 1 1 0 0
Counter
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
13.Briefly explain 3-bit binary ripple up-counter. Also write the truth table and
waveform.
14. Design a modulo-5 up counter (synchronous) using J-K flip flop. (July 15) (10 Marks)

Logic Design 10CS33
15.Design Mod 8 Johnson Counter. (Dec14 / Jan 15) 10 Marks
16. Difference between Asynchronous and Synchronous Counter.

Asynchronous Counter Synchronous Counter

Logic Design 10CS33
1. Clock input is applied to LSB FF. The output 1. Clock input is common to all FF.
of first FF is connected as clock to next FF.
2. All Flip-Flops are toggle FF. 2. Any FF can be used.
3. Speed depends on no. of FF used for n bit . 3. Speed is independent of no. of FF used.
4. No extra Logic Gates are required.

4. Logic Gates are required based on
design.
5. Cost is less. 5. Cost is more.
17. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start
input and done output. The counter should produce done output after
completion of counter in either direction. (July 14.) 10 Marks
18. Draw the logic circuits and the excitation tables for the T, JK flip-flops.
( July 14) 10 Marks

Logic Design 10CS33
19. Design a 3 bit synchronous counter with the help of D flip flop.
(Dec15) 10 Marks
8.Design Mod 4 ring counter. (Dec15) 10 Marks

Logic Design 10CS33
The output of LSB FF is connected as D input to MSB FF.

This is commonly called as Ring Counter or Circular Counter.
The data is shifted to right with each clock pulse.
This counter has four different states.
This can be extended to any no. of bits.
20. Design a synchronous mod 6 up counter using JKflip flop (July 16 ) 10 Marks.
Design of Mod-6 Counter: To design the Mod-6 synchronous counter, contain six counter
states (that is, from 0 to 6). For this counter, the counter design table lists the three flip-flop and
their states as 0 to 6 and the 6 inputs for the 3 flip-flops. The flip-flop inputs essential to step up
the counter from the now to the next state is worked out along with the help of the excitation
table. The needed counter states and the J K inputs essential for counter flip- flops are specified
in the counter design table demonstrated in Table no.1.
Input pulse Counter States Flip-Flop Inputs
A B C JA KA JB KB JC KC
count
0 0 0 0 1 X 0 X 0 X
1 1 0 0 X 1 1 X 0 X
2 0 1 0 1 X X 0 0 X

Logic Design 10CS33
3 1 1 0 X 1 X 1 1 X
4 0 0 1 1 X 0 X X 0
5 1 0 1 X 1 0 X X 1
6(0) 0 0 0
Fig.(b) Karnaugh Maps for JA,KA,JB,KB,JC,KC

Logic Design 10CS33
21. Explain Digital clock with block Diagram. (July 16) 10 Marks

Logic Design 10CS33
Module-5
Counters
1. Explain about all the notation of state machine. (July 16 ) 10 Marks.

Input Variables : External input variables to sequential machine as inputs.
Output Variables : All variables that exit from the sequential machine are output variables.
State : State of sequential machine is defined by the content of memory, when memory is
realized by using FFs.
Present State : The status of all state variable i.e. content of FF for given instant of time t is
called as present state.
Next State : The state of memory at t+1 is called as Next state.
State Diagram : State diagram is graphical representation of state variables represented by
circle. The connection between two states represented by lives with arrows and also indicates
the excitation input and related outputs.
Output Variables : All variables that exit from the sequential machine are output variables.
2. Analyses the following circuit. (July 16 ) 10 Marks.
Zxy y y xy
J2x, K2x, J1y2, K1y2
By substituting the FF inputs in characteristic equation, the next state of FF is obtained in terms

Logic Design
10CS33
of
PS Excitation input Output Z
P QJQKQ
x=0, x=1
Q2 Q1 J2 K2 J1 S The characteristic
K1 x=0, 1 x=0, 1 of equation of JK FF is
(y2 y1) F
F
a
0 1 1 1 Q1J1Q1 K1Q1Q2
n
d Q2J2Q2 K2Q2x
1 1 1 0 e
xt
0 1 0 1 er
n
1 1 0 0 al
in
p
ut.
J1y2Q2, K1yQ 2 2
J2x, K2x, Zxy y y xy 2 2 1 1
Whenx0, zy2 y1andWhenx1, zy1

Logic Design 10CS33
State Diagram of Mealy Network
3. Difference between Mealy Model and Moore Model of Synchronous Sequential

Circuit. (Dec15) 10 Marks
Mealy Model : In Mealy Model the next state is function of external inputs and present
state. The output is also function of external inputs and present state. The memory state
changes with master clock.
Q+ = f(X,Q) Z = g(X,Q)

Logic Design 10CS33
Moore Model : In Moore Model the next state is function of external inputs and present
state. But the output is function of present state. It is not dependent on external inputs.
The no. of FFs required to implement circuit is more compared with Mealy Model,
Q+ = f(X,Q) Z = g(Q)
4. For the given state diagram, draw the state reduction diagram.
(Dec15) 10 Marks
Ans. State table is as shown:
For modified reduced state diagram:

Logic Design 10CS33
5. With neat block diagram compare mealy model of sequential logic system.
(July 15) (8 Marks)
Q+ = f(X,Q) Z = g(X,Q)
6. Draw the ASM chart for vending machine problem using Mealy mlodel.

Logic Design 10CS33
7. For the given state diagram, draw the state reduction diagram.

Logic Design 10CS33
8. Difference between Mealy Model and Moore Model of Synchronous Sequential
Circuit. (Dec14 / Jan 15) 10 Marks

Q+ = f(X,Q) Z = g(X,Q)
Moore Model : In Moore Model the next state is function of external inputs and present
state. But the output is function of present state. It is not dependent on external inputs.
The no. of FFs required to implement circuit is more compared with Mealy Model,

Logic Design 10CS33
Q+ = f(X,Q) Z = g(Q)
9. Analyses the following circuit. (July 14) 10 Marks.
Ans: By substituting the FF inputs in characteristic equation, the next state of FF is obtained in
terms of PS of FF and external input.
The characteristic equation of JK FF is

QJQKQ
Q1J1Q1 K1Q1Q2
PS Excitation input Output Z
x=0, x=1
Q2 Q1 J2 K2 J1
K1
(y2 y1)
x=0, 1 x=0, 1
0 0 0 1 0 1 11
0 1 0 1 0 1 0 0
10 0 1 10 1 1

Logic Design 10CS33
1 1 0 1 10 20 Q2J2Q2 K2Q2x
J1y2Q2, K1yQ 2 2
J2x, K2x, Zxy y y xy 2 2 1 1
Whenx0, zy2 y1andWhenx1, zy1
PS NS O/p Z
x=0 x=1
Q2 Q1 state Q2+ Q1+ state Q2+ Q1+ state X=0 X=1
(y2) (y1)
0 0 A 0 0 A 1 0 C 1 1
0 1 B 0 0 A 1 0 C 0 0
1 0 C 0 1 B 1 1 D 1 1
1 1 D 0 1 B 1 1 D 1 0
State Diagram of Mealy Network

Logic Design 10CS33
0/1
A
1/1 0/0
1/0
D 0/1
B
1/0
1/1
0/1
C
10. Explain with logic diagram 3 bit simultaneous A/D converters. (July 16) 10 Marks
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a
series of comparators, each one comparing the input signal to a unique reference voltage. The
comparator outputs connect to the inputs of a priority encoder circuit, which then produces a
binary output. The following illustration shows a 3-bit flash ADC circuit:

Logic Design 10CS33
Vref is a stable reference voltage provided by a precision voltage regulator as part of the converter
circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at
each comparator, the comparator outputs will sequentially saturate to a high state. The priority
encoder generates a binary number based on the highest-order active input, ignoring all other
active inputs.
11. Explain with logic diagram Single-slope A/D converters ( July 16) 10 Marks
Consider the circuit of Figure 14.1. As the op-amps non-inverting input, V+, istied to
ground, by making use of the golden rules we find that there is a virtual ground at the
inverting input. As long as the circuits input is connected to Vref, the current in the
resistor is Vref/R. This being the case the charge on the capacitor is increasing linearly.
Assuming that the charge on the capacitor is initially zero, the voltage on the capacitor is

Logic Design 10CS33
12. Give performance parameters of DAC or D/A converters.

(Dec15) 10 Marks
Ans. 1. Resolution : Resolution can be defined in two ways
(a) A DAC that can provide number of different analog output values is called resolution.
For a DAC having n-bits

Resolution .
(b) A DAC is which the ratio of change in output voltage resulting from a change of LSB (i.e. 1
least significant bit) at the digital inputs is known as resolution.
Resolution for n-bit DAC is given by
Input-output equation can also be obtained for DAC, if resolution is given
Where, Vo = Resolution x D
Vo = Output voltage
D = Decimal v1ue of the digital input.
2. Accuracy: It is defined as the difference between the actual analog output and the
expected analog output when a given digital input is applied. It is expressed in percentage. In
ideal case,
the accuracy of DAC should be, at worst, of its LSB.
3. Conversion Time or Setting Time: It is the time required for conversion of analog
signal into its digital equivalent. It is dependent on amplifiers output and switches response time.

Logic Design 10CS33
4. Stability: When all the parameters such as gain, linearity error, monotonicity and offset
must be specified over the power supply ranges and full temperature then these parameters
represent the stability of the converter.
5. Monotonicity: If a converter does not miss any step backward during its entire range
stepped by a counter then it is said to have a counter having good monotonicity.
13. An 4 bit DIA converter has an output range of 0 to 1.5 V. Define its resolution.
(Dec15) 10 Marks
Ans. Give n = 4 = number of bits
Full scale output
14. Resolution:
Thus the output voltage can have 16 different values including zero.
15. Resolution:
Thus, an input change of 1 LSB changes the output by 100 mV.
Following fig. shows the D1A converter with op-amp. Calculate the output if the input digital
signal is 1110. Assume 1 binary = +5V.
Ans. Binary data:

Logic Design 10CS33
B3 B2 B1 B0 1110
Let I1, I2 and I3 be the currents flowing through the respective resistors The value of currents
are:
As, the op-amp has a very high input impedance. Thus, the currents I0 to I3 flow through 1K
ohm resistance.

Logic Design 10CS33
14 .Explain the concept of Successive approximation of a A/D converter.

Successive approximation is one of the most widely used popular method due its efficiency The
block diagram of SAR ADC s as shown:
Working: Initially, let us set the MSB bit of SAR register i.e. d1 = 1. It is applied to 4-bit D to A
converter i.e. as 1000. The D/A converter will generate its analog value and send to control logic
The output of control logic is VR. Now at the comparator, there are two inputs VR (Reference
voltage) and VA (Input analog).
If VR > VA output of comparator is low and bit d1 is reset correspondingly.
If VR <VA output of comparator is high and bit d1 remains high.
The same procedure is repeated for all bits i e for d2, d3,. dn, and output may be taken in serial
or parallel manner.
Advantage: The conversion time is fixed as it does not depend upon amplitude of analog input.
15. Draw a binary ladder network for a digital input 1000 and obtain its equivalent
circuit. (July 15) (10 Marks)
Ans Binary ladder D/A converter In a binary ladder D/A converter only two valued resistance R
and 2R are used as shown in diagram

Logic Design 10CS33
The OP amp is an inverting amplifier By solving resistance N/W in parallel and series, finally
voltage at node B is.
3.Comment on the parameters which serve to describe the quality of performance of a

D/A converter. (Dec14 / Jan 15) 10 Marks
. Resolution : Resolution can be defined in two ways
(a) A DAC that can provide number of different analog output values is called resolution.
For a DAC having n-bits

Resolution .
(b) A DAC is which the ratio of change in output voltage resulting from a change of LSB (i.e. 1
least significant bit) at the digital inputs is known as resolution.
Resolution for n-bit DAC is given by

Logic Design 10CS33
Input-output equation can also be obtained for DAC, if resolution is given
Where, Vo = Resolution x D
Vo = Output voltage
D = Decimal v1ue of the digital input.
2. Accuracy: It is defined as the difference between the actual analog output and the
expected analog output when a given digital input is applied. It is expressed in percentage. In
ideal case,
the accuracy of DAC should be, at worst, of its LSB.
3. Conversion Time or Setting Time: It is the time required for conversion of analog
signal into its digital equivalent. It is dependent on amplifiers output and switches response time.
4. Stability: When all the parameters such as gain, linearity error, monotonicity and offset
must be specified over the power supply ranges and full temperature then these parameters
represent the stability of the converter.
5. Monotonicity: If a converter does not miss any step backward during its entire range stepped
by a counter then it is said to have a counter having good monotonicity.
16. With the help of a neat diagram explain parallel A/D converter.
Ans. Parallel A/D is used is much more due to its high speed. The only disadvantage is that its
hardware (no. of comparators) increase with the no. of bits. Va is analog, voltage and VR is
reference voltage.
A 3-bit parallel-comparator AID converter is shown in fig. Va is the analog voltage is be

converted into digital form. The voltage corresponding to full scale is V from which the
reference voltages VR1, VR2. (See Fig.) are generated using the resistor network. The voltage
Va is

Logic Design 10CS33
17. Explain the operation of successive approximation type of ADC

(July 14) 10 Marks
Ans. Successive approximation is one of the most widely used popular method due its efficiency
The block diagram of SAR ADC s as shown:

Logic Design 10CS33
or parallel manner.
18. An 8-bit successive approximation converter (SAC) has a resolution of 15 mV

What
will its, digital output be for an analog input of 2.65 V? (July 14 ) 10
MarksAns. Analog input = 2.65 V Resolution = 15 mV
Now 176 would produce 2.64 V and 177 would produce 2.65 V. Hence VA = 2.65V The digital
result will be (176)10 = (10110000)2
Successive approximation is one of the most widely used popular method due its efficiency The
block diagram of SAR ADC s as shown:

Logic Design 10CS33
or parallel manner.

Assignment Questions
Module 1
1. With the help of neat diagrams explain the operation and drain characteristics of
n-channel depletion type MOSFET. Explain clearly the mechanism of Pinch-off
Condition. Sketch the drain characteristics and define rd.
2. Explain the constructional features of a depletion mode MOSFET and explain its
basic operation.
3. With the help of neat diagram explain the operation of an n-channel enhancement
type MOSFET.
4. Sketch the drain characteristics of MOSFET for different values of VGS and mark
different region of operation.
5. Draw and explain the drain characteristics of n-channel enhancement type
MOSFET.
6. Sketch the graphic symbols for: n-channel JFET, p-channel JFET, n-channel
enhancement type MOSFET, p-channel enhancement type MOSFET, n-channel
depletion type MOSFET and p-channel depletion type MOSFET.
7. Explain the structure of the depletion mode MOSFET. And the D-MOSFET
curves.
8. Explain the active load switching circuit using the MOSFET. Draw its equivalent
circuit and its two terminal curves.
9. With the neat sketch, explain the formation of an inversion layer in a E-
MOSFET. Draw and explain Drain and Transconductance curve of E-MOSFET.
10. Explain how an op-amp can be used as comparator.
11. Draw and explain the working of Schmitt trigger with different threshold levels
LTP and UTP.
12. What is integrator? Derive the expression for an output of op-amp integrator.
13. Draw and explain the basic timing circuit of IC 555. Draw the necessary
waveforms.

14. Draw and explain the function block diagram of IC 555.

Module 2
1. Differentiate between Positive Logic and Negative Logic

2. Using Karnaugh Map,simplify the following boolean expression and give the
implementation of the same using
a. i)NAND gates only(SOP) ii) NOR gates only (POS )
b. F(w,x,y,z)=m(0,1,2,4,5,12,14)+dc(8,10)
3. Simplify the following logic equation using Karnaugh map and give the
implementation of the simplified expression
a. f(w,x,y,z)= m(7)+d(10,11,12,13,14,15)
4. What are Universal gates? Implement the following function using Universal
gates only
5. Find the prime implicants for the boolean expression using Quine Mc-Clusky
method f(w,x,y,z)= m(1,3,6,7,8,9,10,12,13,14)
6. Give the simplified logic equation using Quine-Mcclusky method for the
following
7. Boolean function
a. f(a,b,c,d)= m(0,1,2, 3,10,11,12,13,14,15)
8. What is the purpose of using an Expander with an AND-OR-INVERT gate? Write
a logic circuit of an expandable AND-OR-INVERT gate
9. Simplify the following logic expression using Karnaugh Map and also by Quine-
Mcclusky method
i. i.f(a,b,c,d)= m(1,2,8,9,10,12,13,14)
10. Explain different models for writing Verilog modules.Give an example for each.

Module 3
1. Write a note on Nibble Multiplexers
2. Implement 32:1 multiplexer using 16:1
3. Realize 1:32 Demultiplexer using 1:16 Demultiplexer
4. Write a note on Decoder
5. Write a note on Full Adder
6. Implement BCD to seven segment decoder using PLA
7. Write a note on Priority Encoder

8. Design Decimal to BCD Encoder and Decimal to Octal Encoder.
9. What is a Flip Flop? Discuss the working principle of SR FlipFlop with its truth
table. Also highlight the role of SR Flip flop in switch debouncer circuit
10. With neat schematic diagram of master slave JK-FF,discuss its operation Mention
the advantages of JK-FF over master-slave SR flip-flop.
11. Explain different types of Flip-flops with truth table

Module 4
1. Conversion of SR flipflop to D flipflop
2. Conversion of D flip flop to JK flipflop
3. Find out characteristic equations of S-R FF and J-K FF.
4. With a neat circuit diagram, explain the working of a Serial in Serial out shift
registers.
5. Write a note on applications of Shift registers.
6. Design a 3 bit PISO(DFlip flop)
7. Design two 4 bit serial adder.
8. Design a 4 bit Johnson counter with sate table
9. Design a cyclic mod 6 synchronous binary counter using JK Flip-flop. Give the state
diagram, transition table and excitation table .
10. With a block diagram describe a 3-bit Johnson twisted ring counter. Draw the
sequence diagram and indicate the valid and invalid states.
11. Differentiate between ripple and synchronous counter.
12. Design a synchronous mod 6 up counter using JKflip flop.
13. Explain Digital clock with block Diagram.

Module 5
1. What is accuracy and resolution of the D/A converter? What is the resolution of a
12-bit D/A converter which uses a binary ladder? If the full scale o/p is +10Volts
what is the resolution in volts.
2. What is Binary ladder. Explain binary ladder with digital input of 1000.
3. Explain 2-bit simultaneous A/D converter.Draw the block diagram of a 2-bit A/D
converter.
4. Draw a 4 bit D/A converter using R-2R resistors and explain its working.
5. Find the following for a 12-bit counter type A/D converter using a 1-MHz clock
Maximum conversion time
Average Conversion Time
Maximum Conversion rate
6. Write the circuit diagram, explain the operation of the CMOS NAND gate.
7. Design a CMOS inverter with relevant circuit diagram.
8. With the aid of a circuit diagram, explain the operation of 2-input TTL NAND gate
with Totem-pole output.
9. Explain the operation of 2-input CMOS NOR gate with the help of a circuit diagram
10. Write a note on CMOS characteristics
11. Give six comparisons of CMOS and TTL families.
12. Discuss the features of high speed TTL , Low power and Schottky TTL families.
13. Explain methods for interfacing CMOS devices to TTL devices.
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~ SJBIT

Analog and Digital Electronics

Number of Lecture Hours/Week 04 Exam Marks 80

Total Number of Lecture Hours 50 Exam Hours 03

Course objectives: This course will enable students to

Field Effect Transistors: Junction Field Effect Transistors, MOSFETs, Differences

Flip- Flops: FLIP-FLOP Timing, JK Master-slave FLIP-FLOP, Switch Contact Bounce

Counters: Decade Counters, Presettable Counters, Counter Design as a Synthesis problem,

Graduate Attributes (as per NBA)

VTU Question Paper Solution

Dept. of CSE, SJBIT Page 1

Applying KVL to Collector Emitter loop,

Consider Approx. method as I1> Ib

4. Explain the working of a N-channel E-MOSFET with neat diagram. Explain

Dept. of CSE, SJBIT Page 2

Dept. of CSE, SJBIT Page 3

5. Explain the working of a CMOS inverter.(10 Marks) (June 2015)

6. Explain the construction & working and principle of operation of an n-channel

Dept. of CSE, SJBIT Page 4

Figure: JFET construction

7. Explain the small signal operation of amplifiers. (10 Marks)(June 2015)

Dept. of CSE, SJBIT Page 5

Dept. of CSE, SJBIT Page 6

Figure: Operation of D-MOSFET Figure: Construction of D-MOSFET

Peak Detector Circuit

Dept. of CSE, SJBIT Page 7

Dept. of CSE, SJBIT Page 8

Input / Output Waveform of Peak Detector Circuit

Absolute Value Circuit

Dept. of CSE, SJBIT Page 9

Implementing AND Using only NAND Gates

Implementing OR Using only NAND Gates

NAND Gate is a Universal Gate:

Implementing an Inverter Using only NOR Gate

Dept. of CSE, SJBIT Page 10

Implementing OR Using only NOR Gates

Implementing AND Using only NOR Gates

F(w,x,y,z)=m(0,1,2,4,5,12,14)+dc(8,10) (June/ July 16) 8 Marks

a. NAND Gate (SOP form)

Dept. of CSE, SJBIT Page 11

b. NOR gate (POS form)

3.Explain Duality Theorem? (June/ July 16) 4 Marks

Dept. of CSE, SJBIT Page 12

NAND Gate (SOP form)

Dept. of CSE, SJBIT Page 13

a.NOR gate (POS form)

9.Define Logic. Explain different types of logic. ( July 14) 10 Marks

Dept. of CSE, SJBIT Page 14

10.Differentiate between Analog and Digital Signals. ( July 14) 10 Marks.

Dept. of CSE, SJBIT Page 15

Analog technology records waveforms Converts analog waveforms into set

stream for representation.

Uses continuous range of values to Uses discrete or discontinuous

Can be used in various computing

Analog signal is a continuous signal

Analog clocks indicate time using Digital clocks use numeric

Computer: Analog computer uses changeable

Digital computers represent

Dept. of CSE, SJBIT Page 17

(0, 4, 8,12 ) 0 0(index 0)

(8,10,12,14) 1 0 (index 1)