ALU

Code:
`timescale 1ns/1ps

module ALU4 #(parameter n=3)(

output bit [n+n:0]z,
output bit carry,
input [n:0]b,
input [n:0]a,
input [2:0]sel
);
always@(a,b,sel)
begin
casex(sel)
3'b000:
{z,carry}=a+b;
3'b001:
{z,carry}=a-b;
3'b010:
z=a*b;
3'b011 :
z=a+1;
3'b100:
z=a&b;
3'b101:
z=a|b;
3'b110:
z=a^b;
3'b111:
z=~a;
endcase
end
endmodule

Linear TestBench
`timescale 1ns / 1ps
module ALU8_tb;
bit [6:0]z;
bit carry;
bit [3:0]b;
bit [3:0]a;
bit [2:0]sel;
ALU4 DUT (.*);
initial
begin
#00 a=4'b0010;b=4'b1000;sel=3'b000;
#10 a=4'b0110;b=4'b0100;sel=3'b001;
#10 a=4'b1100;b=4'b0010;sel=3'b010;
#20 a=4'b0011;b=4'b0100;sel=3'b011;
#10 a=4'b0010;b=4'b0100;sel=3'b100;
#10 a=4'b0001;b=4'b1100;sel=3'b101;
#10 a=4'b0111;b=4'b1110;sel=3'b110;
#10 a=4'b1111;b=4'b0110;sel=3'b111;
end
endmodule
Random TestBench
`timescale 1ns/1ps

module ALU8_rtb #(parameter n=3);

bit [n+n:0]z;
bit carry;
bit [n:0]b;
bit [n:0]a;
bit [2:0]sel;

ALU8 dut(.sel,.a,.b,.z,.carry);

initial
repeat(100)
begin
sel=$random();
a=$random();
b=$random();
#20 $monitor("sel=%b,a=%b,b=%b,z=%b,carry=%b",sel,a,b,z,carry);
end
endmodule

Constraint Random TestBench

`timescale 1ns/1ps
module ALU8_crtb #(parameter n=3);
logic [n+n:0]z;
logic carry;
logic [n:0]b;
logic [n:0]a;
logic [2:0]sel;

ALU8 dut(.sel,.a,.b,.z,.carry);

initial
repeat(50)
begin
sel=$urandom_range(3'b000,3'b111);
a=$urandom_range(4'd15,4'd1);
b=$urandom_range(4'd15,4'd1);
#20 $monitor("sel=%b,a=%d,b=%d,z=%d,carry=%d",sel,a,b,z,carry);
end
endmodule

ADD/SUB

Code:
`timescale 1ns/1ps
module adder_subtractor_n_bit #(parameter n=3 )
(
output [n-1:0]sum,
output carry,
input [n-1:0]a,b,
input sel
);
wire [n:0] ic;
wire [n-1:0]b_int;
buf(ic[0],sel);
buf(carry,ic[n]);
genvar j;
generate
for (j=0;j<n;j=j+1)
begin : loop
xor x1(b_int[j],b[j],sel);
fulladder
F1(.sum(sum[j]),.carry(ic[j+1]),.a(a[j]),.b(b_int[j]),.cin(ic[j]));
end
endgenerate
endmodule

TestBench:
`timescale 1ns/1ps
module adder_subtractor_n_bit_tb #(parameter n=3);
bit [n-1:0]sum;
bit carry;
bit [n-1:0]a,b;
bit sel;

adder_subtractor_n_bit dut(.*);

initial
begin
#00 sel=1'b0;a=3'b000;b=3'b000;
#10 sel=1'b0;a=3'b001;b=3'b001;
#10 sel=1'b0;a=3'b010;b=3'b010;
#10 sel=1'b0;a=3'b100;b=3'b100;
#10 sel=1'b0;a=3'b101;b=3'b101;
#10 sel=1'b0;a=3'b110;b=3'b110;
#10 sel=1'b0;a=3'b111;b=3'b111;

#10 sel=1'b1;a=3'b000;b=3'b000;
#10 sel=1'b1;a=3'b001;b=3'b001;
#10 sel=1'b1;a=3'b010;b=3'b010;
#10 sel=1'b1;a=3'b100;b=3'b100;
#10 sel=1'b1;a=3'b101;b=3'b101;
#10 sel=1'b1;a=3'b110;b=3'b110;
#10 sel=1'b1;a=3'b111;b=3'b111;
end
endmodule

Asynchronous _Up _Counter:

Code:
module asychronous_counter
#(parameter n =4,
parameter count = 4'b1010)(
output [n-1:0] q,
input clock,
input clear,
input load,
input [n-1:0] start_t);
wire [n-1:0] internalClear;
wire [n-1:0] internalPreset;
wire count_bool;
assign count_bool = (q == count);
assign internalClear = {n{(clear & ~count_bool)|load}} &
(~load | start_t) ;
assign internalPreset = (load & start_t) |(~load
&{n{1'b0}});
tffASynch TFF1 (.q(q[0]),
.t(1'b1),.clock(clock),.clear(internalClear[0]),
.preset(internalPreset[0]),.enable());
genvar i;
generate
for(i=1;i<n;i=i+1)
begin : loop
tffASynch TFF (.q(q[i]),.t(1'b1),.clock(~q[i1]),
.clear(internalClear[i]),
.preset(internalPreset[i]),.enable());
end
endgenerate
endmodule

Linear TestBench:
module asychronous_counter_tb
#(parameter m = 4, // width
parameter n = 4'b1010 ); // mod n
wire [m-1:0] q;
reg clock;
reg clear;
reg load;
reg [m-1:0] start_t;
integer File;
initial
File = $fopen("modNCounterLoadable_result.txt");
modNcounterLoadable #(m,n)
ModNCounter(.q(q),.clock(clock),.clear(clear),.load(load),
.start_t(start_t));
initial
clock <= 1'b0;
always
#5 clock <= ~clock;
initial
begin
$fmonitor(File, $time, " q = %d, start_t = %d, load = %b,clear =
%b,clock =%b", q, start_t, load, clear,clock);
$monitor($time, " q = %d, start_t = %d, load = %b, clear= %b,
clock=%b", q, start_t, load, clear,clock);
clear = 1'b0;
load = 1'b0;
#5 clear = 1'b1;
#60 start_t = 4'b0101;
#10 load = 1'b1;
#30 load = 1'b0;
end
endmodule

BCD to SEVEN segment :

Code:
`timescale 1ns/1ps
// date 31st of august 2009
module bcdtoseven
( output reg [6:0]o,
input [3:0]in
);
always@(in)
(*full_case*)case(in)
4'b0000:
o=7'b1110111;
4'b0001:
o=7'b0010010;
4'b0010:
o=7'b1011101;
4'b0011:
o=7'b1011011;
4'b0100:
o=7'b0111010;
4'b0101:
o=7'b1101011;
4'b0110:
o=7'b1101111;
4'b0111:
o=7'b1010010;
4'b1000:
o=7'b1111111;
4'b1001:
o=7'b1111010;
endcase
endmodule

Linear TestBench:
`timescale 1ns / 1ps
module bcdtoseven_tb;
bit [6:0]o;
bit [3:0]in;
bcdtoseven DUT (.*);
initial
begin
#00 in=4'b0000;
#10 in=4'b0001;
#10 in=4'b0010;
#10 in=4'b0011;
#10 in=4'b0100;
#10 in=4'b0101;
#10 in=4'b0111;
end
endmodule

Random TestBench
`timescale 1ns/1ps
module sevensegment_tb;
bit [6:0]o;
bit[3:0]in;

sevensegment dut (.o,.in);

initial
repeat(10)
begin
in=$random();
#20 $monitor("in=%b,o=%b",in,o);
end
endmodule

Binary to Gray Converter

Code:
`timescale 1ns/1ps
module binarytogrey #(parameter n=3)(
output logic [n-1:0]out,
input [n-1:0] in,
input sel
);
integer j;
always @(sel,in)
case (sel)
1'b0:begin
out[n-1]=in[n-1];
for(j=n-2;j>=0;j=j-1)
out[j]=in[j]^in[j+1];
end
1'b1:
begin
out[n-1]=in[n-1];
for(j=n-2;j>=0;j=j-1)
out[j]=in[j]^out[j+1];
end
endcase
endmodule

Linear TestBench:
`timescale 1ns / 1ps
module binarytogrey_tb;
logic [2:0] out;
logic [2:0] in;
logic sel;
binarytogrey DUT (.*);
initial
begin
#00 in=3'b000; sel=1'b0;
#10 in=3'b001; sel=1'b0;
#10 in=3'b010; sel=1'b0;
#10 in=3'b011; sel=1'b0;
 #10 in=3'b100; sel=1'b0;
#10 in=3'b101; sel=1'b0;
#10 in=3'b110; sel=1'b0;
#10 in=3'b111; sel=1'b0;

#10 in=3'b000; sel=1'b1;

#10 in=3'b001; sel=1'b1;
#10 in=3'b010; sel=1'b1;
#10 in=3'b011; sel=1'b1;
#10 in=3'b100; sel=1'b1;
#10 in=3'b101; sel=1'b1;
#10 in=3'b110; sel=1'b1;
#10 in=3'b111; sel=1'b1;
end
endmodule

Random TestBench
`timescale 1ns/1ps
module btgtry_tb #(parameter n=3);
bit [n-1:0]out;
bit [n-1:0] in;
bit sel;
btgtry dut(.sel,.in,.out);
initial
repeat(10)
begin
sel=$random();
in=$random();
#20 $monitor("sel=%b,in=%b",sel,in);
end
endmodule

DECODER

Code:
`timescale 1ns/1ps
module decoder1 (
output [3:0]o,
input [1:0]i
);
wire w1,w2;
not n1 (w2,i[1]);
not n2 (w1,i[0]);
and a1(o[3],i[1],i[0]);
and a2(o[2],i[1],w1);
and a3(o[1],w2,i[0]);
and a4(o[0],w2,w1);
endmodule

Linear TestBench:
`timescale 1ns/1ps
module decoder1_tb;
logic [3:0]o;
logic [1:0]i;

decoder1 d1(.*);

initial
begin
#00 i=00;
#10 i=01;
#10 i=10;
#10 i=11;
end
endmodule

Grey Counter

Code:

`timescale 1ns/1ps

module gray

#(parameter n =3)(

output [n-1:0] gray,

input clock,

input reset);

reg sel =1'b1;

reg [n-1:0] count;

always@(posedge clock)

if(reset) count <={n{1'b0}};

else count <= count +1;

btg#(n) BG(.out(gray),.in(count),.sel(sel));

endmodule

`timescale 1ns/1ps

module btgtry #(parameter n=3)(

output reg [n-1:0]out,

input [n-1:0] in,

input sel
);

integer j;

always @(sel,in)

case (sel)

1'b0:begin

out[n-1]=in[n-1];

for(j=n-2;j>=0;j=j-1)

out[j]=in[j]^in[j+1];

end

#60 reset=1'b0;

#100 $stop;

end

endmodule

Linear TestBench:

`timescale 1ns/1ps

module gray_tb #(parameter n =3);

logic [n-1:0] gray;

logic clock;

logic reset;

gray UUT (.*);

integer channel;

initial begin

clock=1;

channel = $fopen("../results/gcount.txt");

$fdisplay(channel, "clock reset gray");

$fmonitor(channel, "%b %b %b ",clock,reset,gray);

end

always #2 clock=~clock;

initial begin

#00 reset=1'b1;

#10 reset=1'b0;

#100 $finish;

end

Random TestBench
`timescale 1ns/1ps
module gray_tb #(parameter n =3);
logic [n-1:0] gray;
logic clock;
logic reset;

gray UUT (.*);

integer channel;

initial begin
clock=1;
channel = $fopen("../results/gcount_rand.txt");
$fdisplay(channel, "clock reset gray");
$fmonitor(channel, "%b %b %b ",clock,reset,gray);
end
always #2 clock=~clock;
initial repeat(13)
begin
reset=$random();
#10 $monitor( "%b %b ",reset ,gray);
#10 $display(" reset ,gray");
end
endmodule

Constraint Random TestBench

`timescale 1ns/1ps
module gray_tb #(parameter n =3);
logic [n-1:0] gray;
 logic clock;
logic reset;

gray UUT (.*);

integer channel;

initial begin
clock=1;
channel = $fopen("../results/gcount_urand.txt");
$fdisplay(channel, "clock reset gray");
$fmonitor(channel, "%b %b %b ",clock,reset,gray);
end
always #2 clock=~clock;
initial repeat(13)
begin
reset=$urandom_range(1'd1,1'd0);
#10 $monitor( "%b %b ",reset ,gray);
#10 $display(" reset ,gray");
end
endmodule

JOHNSON COUNTER

Code:
`timescale 1ns/1ps
module johnson #(parameter n= 4)(
output [n:0]y,
input clk,
input clear,
input load,
input [n:0]data,
input enable
);
reg [n:0] temp;
always@(posedge clk,posedge clear)
if(clear) temp <= {n{1'b0}};
else if(enable)
if(load)
temp <= data;
else

temp<={~temp[0],temp[n:1]};
assign y=temp;
endmodule

Random TestBench

`timescale 1ns/1ps
module johnson_tb #(parameter n=4);
bit [n:0]y;
bit clk;
bit clear;
bit load;
bit [n:0]data;
bit enable;
johnson DUT(.*);
initial
repeat(20)
begin
enable=$random();
data=$random();
load=$random();
clear=$random();
clk=$random();
#30
$monitor("enable=%b,data=%b,load=%b,clear=%b,clk=%b,y=%b",enable,data,load,clear,clk
,y);
end
endmodule

JK FF with asynchronous control signals

Code:
`timescale 1ns/1ps
module jkff(
output reg y,
input clk,
input clear,
input preset,
input j,k
);
always@(posedge clk,posedge clear,posedge preset)
if (clear)
y=1'b0;
else if(preset)
y=1'b1;
else
begin
case({j,k})
2'b00:y<=y;
2'b01:y<=0;
2'b10:y<=1;
2'b11:y<=~y;
//y=(t==1)?y:~y;
endcase
end
endmodule
Linear TestBench:

`timescale 1ns/1ps
module jkff_tb;
logic y;
logic clk;
logic clear;
logic preset;
logic j,k;
jkff dut(.*);

initial
begin
clk=0;
#00 clear=1;
end
always #10 clk=~clk;
initial
begin
#00 clear=0;j=1'b0;k=1'b0;
#00 clear=0;j=1'b0;k=1'b1;
#00 clear=0;j=1'b1;k=1'b0;
#00 clear=0;j=1'b1;k=1'b1;

#00 clear=1;j=1'b0;k=1'b0;
#00 clear=1;j=1'b0;k=1'b1;
#00 clear=1;j=1'b1;k=1'b0;
#00 clear=1;j=1'b1;k=1'b1;
end
endmodule

4:1 MUX

Code:
`timescale 1ns/1ps
// date 31st of august 2009
module mux41(
output reg z,
input [3:0]in,
input [1:0]sel
);
always@(in,sel)
casex (sel)
2'b00:z=in[0];
2'b01:z=in[1];
2'b10:z=in[2];
2'b11:z=in[3];
endcase
endmodule
Linear TestBench:

`timescale 1ns / 1ps

module mux41_tb;
logic z;
logic [3:0]in;
logic [1:0]sel;
mux41 DUT (.*);
initial
begin
#00 in=3'b1010; sel=1'b00;
#10 in=3'b1010; sel=1'b01;
#10 in=3'b1010; sel=1'b10;
#10 in=3'b1010; sel=1'b11;
end
endmodule

Random TestBench
`timescale 1ns / 1ps
module mux41_tb;
logic z;
logic [3:0]in;
logic [1:0]sel;
mux41 DUT (.*);
initial
repeat(25)
begin
sel=$random();
in=$random();

#20 $monitor("sel=%b,in=%b,z=%b",sel,in,z);
end
endmodule

Constraint Random TestBench

`timescale 1ns / 1ps
module mux41_tb;
logic z;
logic [3:0]in;
logic [1:0]sel;
mux41 DUT (.*);
initial
repeat(25)
begin
sel=$urandom_range(2'b11,2'b00);
in=$urandom_range(4'b1111,'b0000);

#20 $monitor("sel=%b,in=%b,z=%b",sel,in,z);
end
endmodule

8:1 MUX
`timescale 1ns/1ps
module mux81(
output logic z,
input [7:0]in,
input [2:0]sel
);
always@(in,sel)
casex (sel)
3'b000:z=in[0];
3'b001:z=in[1];
3'b010:z=in[2];
3'b011:z=in[3];
3'b100:z=in[4];
3'b101:z=in[5];
3'b110:z=in[6];
3'b111:z=in[7];
endcase
endmodule

Linear TestBench:
`timescale 1ns / 1ps
module mux81_tb;
logic z;
logic [7:0]in;
logic [2:0]sel;
mux81 DUT (.*);
initial
begin
#00 in=3'b10101010; sel=1'b000;
#10 in=3'b10101010; sel=1'b001;
#10 in=3'b10101010; sel=1'b010;
#10 in=3'b10101010; sel=1'b011;

#00 in=3'b10101010; sel=1'b100;

#10 in=3'b10101010; sel=1'b101;
#10 in=3'b10101010; sel=1'b110;
#10 in=3'b10101010; sel=1'b111;

end
endmodule

Random TestBench
`timescale 1ns / 1ps
module mux81_tb;
logic z;
logic [7:0]in;
logic [2:0]sel;
mux81 DUT (.*);

initial
 repeat(25)
begin
sel=$random();
in=$random();

#20 $monitor("sel=%b,in=%b,z=%b",sel,in,z);
end
endmodule

Constraint Random TestBench

`timescale 1ns / 1ps
module mux81_tb;
logic z;
logic [7:0]in;
logic [2:0]sel;
mux81 DUT (.*);

initial
repeat(25)
begin
sel=$urandom_range(8'b11111111,8'b00000000);
in=$urandom_range(3'b111,3'b000);

#20 $monitor("sel=%b,in=%b,z=%b",sel,in,z);
end
endmodule

Priority Encoder