The QUICK VHDL

Manual

Danny Savory
 Forward

VHDL is a difficult language to learn and become proficient in, with many subtleties that can lead
to unforeseen problems. A design that simulates well will not necessarily syntheze properly to an
FPGA.

This manual is intended for use as a quick reference to someone already familiar with VHDL. It is
NOT a beginner’s guide to VHDL or FPGA design. Quick Reference pages are located in the front,
and more in-depth summaries are located in the back.

I hope it will be useful to you as a hardware designer to avoid common errors that arise from
uncertainty with VHDL syntax or conventions.

--danny savory

i
 Contents
Quick References
concurrent conditional statement
signal select statement
signal declaration
constant declaration
entity declaration
architecture declaration ___________________________________________ page 3

component declaration
component instantiation
process declaration
variable declaration _________________________________________________ page 4

function declaration
case statement
if statement
numerical representation
for loop statement
for generate statement _____________________________________________ page 5

type casting
custom type declaration ___________________________________________ page 6

1
 Contents
Quick Summaries
process summary __________________________________________________________ page 7

component summary
concurrent select statement summary
function summary
for loop summary
for generate summary
data type summary ____________________________________________________ page 8

type declaration summary

case statement summary ___________________________________________ page 9

Glossary ______________________________________________________________________ page 10

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 Quick Reference
Identifier declaration Entity declaration
• A-Z, underscores, 0-9 ENTITY entityName IS
• Must begin with letter PORT(
• Last character cannot be underscore portName : IN/OUT/INOUT *type*;
• Two underscores in a row not allowed portName2 : IN/OUT/INOUT *type*;
...
portNameFinal : IN/OUT/INOUT *type*
);
GENERIC(
Concurrent Conditional genericName1 : *type* := <initVal>;
signal1 <= value1 WHEN condition1 ELSE genericName2 : *type* := <initVal>;
value2 WHEN condition2 ELSE ...
... genericNameFin : *type* := <initVal>
);
finalValue; END ENTITY/entityName;

Concurrent Select
Architecture declaration
WITH specSignal SELECT
assignedSignal <= value1 WHEN condition1, ARCHITECTURE archName OF
value2 WHEN condition2, entityName IS
...
finalValue WHEN finalCond; component instantiations...
function declarations...
signal declarations...
constant declarations...
Signal declaration variable declarations...
type declarations...
SIGNAL signalName : *type* := <initVal>;
BEGIN

sequential statements...
Constant declaration concurrent statements...

CONSTANT constantName : *type* := <initVal>; END ARCHITECTURE;

3
 Quick Reference
Component declaration Component Instantiation
COMPONENT componentName IS
(with imported library)
PORT( componentName : specificUnitName
portName : IN/OUT/INOUT *type*; GENERIC MAP(
portName2 : IN/OUT/INOUT *type*; declaredGeneric1 => genericValue1,
... declaredGeneric2 => genericValue2,
portNameFinal : IN/OUT/INOUT *type* ...
); lastDeclaredGeneric => lastValue
GENERIC( )
genericName1 : *type* := <initVal>; PORT MAP (
genericName2 : *type* := <initVal>; declaredPort1 => connection1,
... declaredPort2 => connection2,
genericNameFin : *type* := <initVal> ...
); lastDeclaredPort => lastConnection
END COMPONENT; );

Component Instantiation
Process declaration specificUnitName : ENTITY libraryName.
entityName(architectureName)
PROCESS (sensitivityList...) GENERIC MAP(
VARIABLE var1, var2, ... lastVar : *type* declaredGeneric1 => genericValue1,
BEGIN declaredGeneric2 => genericValue2,
...
sequential statements... lastDeclaredGeneric => lastValue
)
END PROCESS; PORT MAP (
declaredPort1 => connection1,
declaredPort2 => connection2,
...
lastDeclaredPort => lastConnection
Variable declaration );

VARIABLE varName : *type* := value;

4
 Quick Reference
Function Declaration If statement
FUNCTION functName (parameterList) RETURN *type* IS IF signalExpression1 THEN
VARIABLE var1, var2, ... lastVar : *type* sequentialStatement1;
BEGIN ELSIF signalExpression2 THEN
sequentialStatement2;
sequential statements... ...
ELSE
RETURN (statement); finalSequentialStatement;
END IF;
END;

Case statement For loop

CASE signalName IS
WHEN val1 => FOR indexVar IN upperLimit LOOP
sequentialStatement1; sequentialStatement1;
WHEN val2 => sequentialStatement2;
sequentialStatement2; ...
... finalSequentialStatement;
WHEN finalVal => END LOOP;
finalSequentialStatement;
END CASE;

Numerical representation For-Generate statement

13E5 (1,300,000) forGenerateBlockName:
1300000 (1,300,000) FOR indexVar IN upperLimit GENERATE
1_300_000 (1,300,000) concurrentStatement1;
1.3E6 (1,300,000) concurrentStatement2;
13.0 (13) ...
2#01101# (13) binary finalConcurrentStatement;
16#0D# (13) hexadecimal END GENERATE;

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 Quick Reference
Common Type Casting Type Declaration
std_logic_vector ---> unsigned TYPE customTypeName IS
unsigned(stdLogicVectorName); (typeName1, typeName2, ..., finalTypeName);

std_logic_vector ---> signed

signed(stdLogicVectorName);

unsigned ---> std_logic_vector

std_logic_vector(unsignedName);

unsigned ---> signed

signed(unsignedName);

signed ---> std_logic_vector

std_logic_vector(signedName);

integer ---> signed

to_signed(integerName, sizeOfSigned);

integer ---> unsigned

to_unsigned(integerName, sizeOfUn
signed);

integer ---> std_logic_vector

1) integer ---> signed/unsigned
2) signed/unsigned ---> std_logic_vector

signed ---> integer

to_integer(signedName);

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 Quick Summaries
Process summary
• Processes consist of sequential state-
ments.
• A process sensitivity list must contain
signals on the right side of assignment
statements, as well as signals in test
expressions (if-else statements, case
statements)
EXAMPLE 1:
process(foo, bar, clk)
begin
if(clk’event and clk = ‘1’) then
foo <= candy;
bar <= ‘1’;
foo <= ‘1’;
end if;
end process;
The above sensitivity list is incomplete as it is
missing the signal “candy” which foo is being
assigned.
• Incomplete sensitivity lists result in
“latched” behavior and designs that will
not synthesize properly.
• The last sequential assignments in a
process are executed over previous
sequential assignments. For example,
after executing the process in example 1,
the signal “foo” will be assigned to ‘1’, not
“candy”.
• All statements within a process are exe-
cuted at the end of the process, with “old”
signal values. (Entire process treated as
one unit).
EXAMPLE 2:
foo <= “0110”;
burger <= “0000”;
process(foo, bar, clk, burger)
begin
if(clk’event and clk = ‘1’) then
foo <= burger;
bar <= foo;
end if;
end process;
At the end of the above process, the signal
“bar” will be assigned “0110”, the “old” value
of foo, not “0000”, the value assigned in the
process. This occurs even though the as-
signment “foo <= burger;” occurs before “bar
<= foo”.
• Concurrent conditional and select signal
assignments cannot be placed inside a
process.
• Complex processes are difficult to syn-
thesize. Generally, it is better to use
multiple small processes to accomplish a
task than one gigantic one.

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 Quick Summaries
Component summary For loop Summary
• Componants can be imported with appro-
priate libraries and instantiated as a way • For loops are almost impossible to synthe-
to reuse design modules. size. When using them, try to keep them
as simple as possible.
• Generics are optional with components.

For-Generate Summary
Concurrent Select Summary • For-Generate statements are useful in
• The select signal condition list must be ex- creating repetitive architecture, but the
haustive (all possible signal conditions must number of times the loop will iterate must
be covered). be declared before the design can be syn-
thesized (i.e. it cannot be declared during
• The “OTHERS” keyword can be used to cover run time).
any and all remaining possible signal condi-
tions.
Data type summary
EX:
• Some common IEEE standard data
WITH specSignal SELECT types are: std_logic, unsigned,
assignedSignal <= value1 WHEN condition1, signed, and std_logic_vector.
value2 WHEN condition2,
... • To use them, you must import the ap-
finalValue WHEN OTHERS; propriate libraries:

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
Function Summary • Many data types are not directly com-
• Functions can be declared in the declara- patable with each other, and casting
tion section of an architecture. is required to accomplsh these as-
signments.
• Difficult to synthesize; should be used only
for frequently used, simple routines.

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 Quick Summaries
Type Declaration Summary Case Summary
• Custom type declaration is useful in constructing • Case statement signal values must be
finite state machine states. exhaustive. The keyword “OTHERS” may
be used to cover any and all remaining
EX: possible conditions.

TYPE myStateType IS EX:

(defaultState1, nextState2, ..., finalState);
CASE signalName IS
SIGNAL currentSTATE, nextSTATE : myStateType; WHEN val1 =>
sequentialStatement1;
...
WHEN OTHERS =>
finalSequentialStatement;
END CASE;

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 Glossary
Architecture - The “behavior” of an ENTITY. Defines what an ENTITY does with input and how it
outputs the results.

Concurrent statements - Statements that do not occur in a sequence. They are always run-
ning. Nonsequential.

Entity - One of the basic building blocks in VHDL. Essentially a “black box” with inputs and out-
puts. Requires an ARCHITECTURE to define its behavior.

FPGA - Field Programmable Gate Array. A board with “programmable” hardware. Program-
mable connections between logic gates (“slices”) can be specified and changed using an HDL.

HDL - Hardware Description Language. A type of programming language that describes hard-
ware (circuits). Differs from typical programming languages like C, C++, and Java in that it must
describe concurrent activities, hardware timing delays, and the connectibility of different blocks of
hardware.

Simulation - Executing a particular design on a computer.

Synthesis - Downloading and executing a particular design to a board for actual hardware imple-
mentation.

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Feel free to copy it and pass it on,

but don’t be a jerk and sell it.

Copyright © 2010 by Danny Savory