EE370

Digital Electronics

L13: Logic synthesis _part-3

B. Mazhari
Dept. of EE, IIT Kanpur

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 Y = a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g

a
d 1
f

Already minimized 2 7

c
e 6
f
g

Hardware required :
6 3-i/p AND gate
1 7-i/p OR gate

(or 7 gates with average Fan-in of 3.57 )

25 wires (19 literals, 6 internal wires)
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 A Multi-Level Representation
a
d 1 1 2 3
f
a
2 7
b
c

d
c
e
e 6
f f
g g

Hardware required :
6 3-i/p AND gate Hardware required : 2 3-i/p
gates, 2 2-i/p gates
1 7-i/p OR gate (or 4 gates with average Fan-in
of 2.5 )
(or 7 gates with average 11 wires (7 literals, 4 internal
Fan-in of 3.57 ) wires)
25 wires (19 literals, 6
internal wires)
Y = (a+b+c). (d+e). f + g
Y = a.d.f + a.e.f + b.d.f + b.e.f +
217
c.d.f
B. + c.e.f
Mazhari, IITK + g
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Multi-Level Minimization

Y = a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g

Y = (a+b+c). (d+e). f + g

The basic operation involved in obtaining such a

representation is factoring or a kind of Boolean division

Y=D.Q+R

D is the divisor , Q the quotient and R the remainder.

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Multi-Level Minimization

Y = a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g

Y = (a+b+c). (d+e). f + g

The basic operation involved in obtaining such a

representation is factoring or a kind of Boolean division

Y=D.Q+R

D is the divisor , Q the quotient and R the remainder.

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 a.f + b.f + c.f
a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g
(d+e)
a.d.f + a.e.f
b.d.f + b.e.f + c.d.f + c.e.f + g

b.d.f + b.e.f
c.d.f + c.e.f + g

c.d.f + c.e.f
g

Y = a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g = (d+e) .(af+bf+cf)+g

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 a.d = (1+b).a.d = a.d+b.a.d

d a.d + c.d
a.d+ b.c.d + e
(a+b)
a.d
a.d++b.a.d
b.d
b.c.d + e

a.c.d + b.c.d
e
a.d+ b.c.d + e = (a+b).(a.d+c.d)+e
= (a+b).(a+c).d+e
1 3i/p, 3 2i/p gate
2 3i/p, 1 2i/p gate
F1 = a.d+ b.c.d + e
Is there any gain ? F2 = (a+b)
F3 = (a+c)..
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 Y = a.d.f + a.e.f + b.d.f + b.e.f + c.d.f + c.e.f + g

Y = (d+e). (a.f+b.f+c.f) + g

D R
Q
f .(a+b+c)

Key to minimization is the selection of the right divisor

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 f = a.b + a.c.d + a.c.e + b.c.e + b.c.d

Subsets of function F: f = (b+c.d) a+(e.(a+b)+b.d).c

1. a.b+a.c.d a.(b+c.d)
2. a.b+a.c.e a.(b+c.e)
3. a.b+b.c.e b.(a+c.e)
4. a.b+b.c.d
5. a.c.d+a.c.e ac.(d+e)
6.
7. f = (a+b). c.(d + e) + a.b

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 Alternative Representation
Y = a.b+b.c+c.d+d.a

Hardware required : Hardware required : 3 2-i/p

4 2-i/p AND gate gates,
6 wires (4 literals, 2 internal
1 4-i/p OR gate wires)

(or 7 gates with average Fan-

in of 2.4 )
12 wires (8 literals, 4 internal SoP PoS
wires)
Y = a.b+b.c+c.d+d.a Y = (a+c). (d+b)
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 0 0 1 0
0 0 1 1
1 1 1 1
0 1 1 0

Y = a.b+b.c+c.d+d.a Y = (a+c). (d+b)

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Example-3

f1 x1 x2 x3 x2 x3 x4 x5
f 2 x1 x5 x4 x5
f 3 x1 x2 x4

f1 x2 x3 ( x1 x4 ) x5
f 2 ( x1 x4 ) x5
f 3 ( x1 x4 )x2

Factoring allows Sharing across expressions

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Technology Mapping

x1
x2

x3
x4
x5

x6

Gate Area Cost Delay

Inverter 0.65 0.8

Two input NAND 1 1
Three input NAND 1.3 1.3
Y AB C AND-OR-Invert 1.3 1.9
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 180nm technology

1.3
1 0.8

1.87 1.6
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Trivial covering

Total area cost =5*0.65+5=8.25 Delay = 0.8*2+3=4.6

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 Can you see an AOI gate in there?
Y AB C

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 Expand each library element in terms of NAND-NOT
network

a
b

c
NAND-3

a
b

AOI

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 NAND-3

3.8

Total area cost =4*0.65+3+1.3=6.9

a
b Delay = 0.8+1.3+1=3.1
c
NAND-3

a
b

c
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 NAND-3

a
b

c
NAND-3

a
b

c
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 NAND-3

AOI
a
b
Total area cost =4*0.65+1.3+1.3+1=6.2
c
Delay = 0.8+1.9+0.8+1=4.5
NAND-3

a
b

AOI
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 2
4

1 5 6 7

1 Libraray

4 NAND-3

6 6,5,4,3 AOI

7,6,5 235
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