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FLIP-FLOP

The most important memory element is the flip-flop, which is made up of an assembly of logic
gates. Even though a logic gate by itself has no storage capability, several logic gates can be
connected together in ways that permit information to be stored. Flip-flops are the basic building
blocks of most sequential circuits.

A flip-flop (FF), known more formally as bistable multivibrator, has two stable states. It can
remain in either of the states indefinitely. Its state can be changed by applying the proper
triggering signal. It is also called a 1-bit memory.

The figure below shows the general flip-flop symbol

Fig: Flip Flop symbol

The flip-flop has two outputs, labeled Q and . The Q output is the normal output of the FF and
is the inverted output. The state of the FF always refers to the normal output Q.

A FF is said to be HIGH state or logic 1 state or SET state when Q = 1, and in LOW state or
logic 0 state or RESET state or CLEAR state when Q =0.

Latch
The term latch is used for certain flip-flops. It refers to non-clocked flip-flops because these
flip-flops latch on to a 1 or a 0 immediately upon receiving the input pulse called SET or
RESET. They are not dependent on the clock signal for their operation.
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Types of Flip-Flops

The different types of flip-flops are

S-R Flip-Flop
D Flip-Flop
J-K Flip-Flop
T Flip-Flop

S-R Flip-Flop

The logic diagram for S-R flip-flop is shown below

Fig: Logic diagram for S-R flip-flop

The truth table of S-R flip-flop is

S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Invalid

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The analysis of the operation

S = 0, R = 0

It has no effect on the output state. Q and will remain in whatever state they were prior to the
occurrence of this input condition.

S = 0, R = 1

This will always reset Q = 0, where it will remain even after RESET returns to zero.

S = 1, R = 0

This will set Q = 1, where it will remain even after SET returns to 0.

S = 1, R = 1

It produces Q = = 0. This state is erratic and unpredictable.

The characteristic table of S-R flip-flop is

S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X

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The characteristic equation of S-R flip-flop is

The excitation table of S-R flip-flop is

Present State Next State Required Inputs

Q(t) Q(t+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

D Flip-Flop

D flip-flop is constructed from S-R flip-flop. In S-R flip-flop, when S and R are connected
inversely then we get D flip-flop. It is having only one input.

Fig: Logic diagram for D flip-flop

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The truth table of D flip-flop is

D Q(t+1)
0 0
1 1

The characteristic table of D flip-flop is

D Q(t) Q(t+1)
0 0 0
0 1 0
1 0 1
1 1 1

The characteristic equation of D flip-flop is

The excitation table of D flip-flop is

Present State Next State Required Input

Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 0

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J-K Flip-Flop

The logic diagram for J-K flip-flop is shown below

Fig: Logic diagram for J-K flip-flop

The truth table of J-K flip-flop is

J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1

The analysis of the operation

J = 0, K = 0

It has no effect on the output state. Q and will remain in whatever state they were prior to the
occurrence of this input condition.

J = 0, K = 1
This will always reset Q = 0, where it will remain even after RESET returns to zero.
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J = 1, K = 0
This will set Q = 1, where it will remain even after SET returns to 0.

J = 1, K = 1
In this mode, the flip-flop toggles.

The characteristic table of J-K flip-flop is

J K
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Q(t) Q(t+1)
0 0
1 1
0 0
1 0
0 1
1 1
0 1
1 0

The characteristic equation of J-K flip-flop is

The excitation table of J-K flip-flop is

Present State Next State Required Inputs

Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

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T Flip-Flop

T flip-flop is constructed from J-K flip-flop. In J-K flip-flop, when J and K are connected
directly, then we get T flip-flop.

Fig: Logic diagram for T flip-flop

The truth table of T flip-flop is

T Q(t+1)
0 Q(t)
1

The characteristic table of T flip-flop is

T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

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The characteristic equation of T flip-flop is

The excitation table of T flip-flop is

Present State Next State Required Input

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

Race Around Condition

For the J-K flip-flop with J = K = 1, if the width of the clock pulse tp is too long, the state of
the flip-flop will keep on changing from 0 to 1, 1 to 0, 0 to 1 and so on, and at the end of the
clock pulse, its state will be uncertain. This phenomenon is called the race around condition.

The outputs Q and will change on their own if the clock pulse width tp is too long
compared with the propagation delay of each NAND gate.

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Conversion of Flip-Flops

The flip-flops can be converted from one to another by following some steps as

1. Write the characteristics table of required FF.

2. Next write the excitation table of the available or given FF.
3. Finally, solve the K-Map for the given FF as input and the required FF as output.

SR-FF to other FFs

To understand the above steps we will solve one example. Rest can be solved by following the
same steps.

SR-FF to JK-FF

Here, required FF = JK

Given FF = SR

CHARACTERISTIC TABLE EXCITATION TABLE

J K
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Qn Qn+1
0 0
1 1
0 0
1 0
0 1
1 1
0 1
1 0
S R
0 X
X 0
0 X
0 1
1 0
X 0
1 0
0 1

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Solving the K-Map for S and R with J, K and Qn as input we get

Fig: SR-FF to JK-FF

SR-FF to D-FF

SR-FF to T-FF

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JK-FF to other FFs

JK-FF to SR-FF

JK-FF to D-FF

JK-FF to T-FF

D-FF to other FFs

D-FF to SR-FF

D-FF to JK-FF

D-FF to T-FF

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T-FF to other FFs

T-FF to SR-FF

T-FF to JK-FF

T-FF to JK-FF

Applications of Flip-Flops

Parallel data storage

Serial data storage
Transfer of data
Serial-to-Parallel conversion
Counting
Frequency Division

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