Code: R7221004

R07
B.Tech II Year II Semester (R07) Supplementary Examinations June 2014
DIGITAL IC APPLICATIONS
(Electronics and Instrumentation Engineering)
Time: 3 hours Max. Marks: 80
Answer any FIVE questions
All questions carry equal marks
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1 (a) Using suitable sketches and equations explain the steady state electrical
behavior of CMOS logic gate.
(b) List out the characteristics of CMOS logic families and explain their importance.

2 (a) Draw the circuit of the basic gate of TTL logic family and explain its operation
using required waveforms.
(b) Using neat sketches explain the interfacing of CMOS and TTL.

3 (a) Enlist the data types supported by VHDL and explain in detail about each data
type.
(b) What are the different modeling styles of VHDL and compare them.

4 (a) What is a package in VHDL and how it is used in VHDL codes along with its
syntax? What are the various pre-defined packages available in VHDL?
Compare packages and libraries.
(b) Write VHDL code for a full adder circuit using half adder and gates and support
the circuit thus implemented using logical equations.

5 Write data flow model, behavioral model using case statement and if-then-else
statement and structural model for an 8:1 multiplexer.

6 (a) Write VHDL code for D-Flip Flop and JK Flip Flop long with neat sketches.
(b) Using required sketches design a decade counter and write its VHDL code.

7 (a) What is parity? Describe how an odd parity can be generated for n-bit input
specifications and draw the circuit of the same and also write its VHDL code.
(b) Design a barrel shifter for 8-bit using three control inputs. Write a VHDL
program for the same in data flow style.

8 (a) Draw the internal structure of ROM and explain its operation using timing
diagrams.
(b) Using neat sketches explain the operation and internal structure of DRAM using
timing diagrams.

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