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Conference Agenda: Thursday, September 7

TRACK 1 TRACK 2 TRACK 3 TRACK 4 TRACK 5
System to Signoff: System to Signoff: System to Signoff: Custom and Analog Design: Custom and Analog Design:
Time Digital Implementation Front-End Design Signoff and Power Analysis Verification Implementation
Room: Grand Victoria B Room: Grand Victoria A Room: Robusta Room: Arabica Room: Boulangerie

08:45 - 09:15 Registration

Welcome
09:15- 09:40
Jaswinder Ahuja, Corporate Vice President and India Managing Director, Cadence

Cadence Technology Keynote

09:40- 10:10
Vinod Kariat, Vice President - R&D, Custom and PCB Group, Cadence

Guest Keynote
10:10 -10:40
Venugopal Puvvada, Vice President - Engineering, Qualcomm

10:40 - 11:00 Tea Break

11:00- 11:30 Technology Update

Invited Talk: (Arm) Technology Update Technology Update

11:30 12:00 Getting The Best PPA On The Latest Arm Processors in 16FFC
Process Using Cadence Digital and Signoff Technologies

Room Turnaround - 15 minutes Proceed to Robusta Room

DIG01 (Broadcom) FED01 (Microsemi) 3A - Signoff CAV01 CAI01 (Applied Micro Circuits)
12:15 - 12:45 12:15 - 12:45 INVITED PAPER: (MACOM) Automated DRC Cleaning Using
Top-Down Multi-Level Early Timing Predictability Using SO01 (Arm) Pushing the Limits Efficient and Faster Method of Virtuoso IPVS Results
12:00 - 12:30 Hierarchical Approach for Genus Physical of Power Efficiency with Arm Using Memory Characterization
Session 1 80M+ Instance 16FF+ Network Cortex-A55 CPU Optimized with and Circuit Simulation
Processing Chip Tempus Signoff Technologies for the AOCV
Data Generation for Memory
Compilers

DIG02 (Qualcomm) FED02 (Texas Instruments) SO02 (Open-Silicon) CAV02 (Sankalp Semiconductor) CAI02 (STMicroelectronics)
12:30 - 13:00 12:45 - 13:15 12:45 - 13:15 HBM2 Based 2.5D System - GUI-Based Front End for Liberate, ModGen and SPD: A Game
Surgical Design Closure of a Very Low Pin-Count Scan Architecture Planning, Implementation, and Faster/Robust Way to Setup a Changer in NVM Developments
Session 2 Signoff Liberate Workarea
Large High-Performance Design Using Cadence Elastic
Compression

Lunch Lunch
13:15 - 14:00 13:00 - 14:00

DIG03 (SilabTech) FED03 (Cypress Semiconductor) SO03 (Microsemi) CAV03 (Texas Instruments) CAI03 (Rambus)
14:00 - 14:30 Fast Floorplan Prototyping for Challenges of Implementing Timing Optimization for a Better Highly Efficient and Metric- PDK Agnostic Framework for
Mixed-Signal Design Using Zero Pin Retention with Cadence Signoff Driven Analog Verification Design Database Porting/
Session 3 Innovus Tools: Gain of Using NOR-Based Methodology Translation to 7nm in Cadence
Isolation Virtuoso Platform

DIG04 (GLOBALFOUNDRIES) FED04 (NXP) SO04 (Microsemi) CAV04 (Arm) CAI04 (STMicro)
14:30 - 15:00 PipeLine Latch/Flop Placement A Novel Approach to Implement INVITED PAPER: Using Pegasus Thermal Analysis Based Faster and Constraint Driven
Methodology QoR Conformal ECO by Divide and Solution for Advanced Node Electromigration Flow Using Method of Implementing
Session 4 Improvement Concur Method Physical Verification Cadence Technologies Electrically Aware Layout Using
Virtuoso EAD

DIG05 (Microsemi) FED05 (NXP) SO05 (Cypress) CAV05 (Texas Instruments) CAI05 (Sankalp Semiconductor)
15:00 - 15:30 PnR Methodology for High- Intelligent Clock Gating Insertion DMMMC and AOCV Based PBA Simulator Agnostic Techniques Layout Versus XLS (LVX) Tool
Performance Crossbar Switch Scheme for Low-Power Digital Signoff of Next Generation and AMS-XPS-MS Simulator for
Session 5 Design Programmable SoC Using Tempus Faster System-Level AMS
Timing Signoff Solution Co-Simulation

15:30 - 16:00 Tea Break

DIG06 (Texas Instruments) FED06 (Lattice 3B - Power Analysis CAV06 (NXP) AI06 (STMicro)
Techniques for Area and Power Semiconductor/Invecas) AVFoRge - Platform For IO Layout Productivity Gain in
16:00 - 16:30 Optimization for Complex Clock Parallel Smartscan Test Solution PA01 (Analog Devices) Automating Analog/Mixed-Signal 28FDSOI Device Level Routing
Session 6 Architecture Designs for Complex Low-Power Designs Beyond Power Analysis: Using IP Signoff Using VSR Pin-to-Trunk
Joules for RTL Power Estimation
and Improve Design Power

DIG07 (MediaTek) FED07 (Texas Instruments) PA02 (Silabtech) CAV07 (Texas Instruments) CAI07 (NXP)
16:30 -17:00 Achieving Sustainable Scalable Scan Architecture for Silicon Proven Power Analysis Importing Analog/AMS Implementation of a PCell
Performance (W/GHz) on Multiple Scan Configurations in Methodology for Mixed Signal IP Simulation Data to Python for Feature Above the pCell
Session 7 Arm Core Using Advanced a Single SoC Using Voltus Faster Computations Using Hierarchy Using Add-On PCell in
Methodologies and Cadence Tool Cadence SRR Libraries SKILL, Virtuoso Solutions

DIG08 (Texas Instruments) FED08 (Texas Instruments) PA03 (STMicro) CAV08 (Arm) CAI08 (Texas Instruments)
17:00 - 17:30 Achieving Low Power With Low Cost High Performance Power Signoff for Automotive Spectre-Incisive COSIM for Accurate Quantus-Based
Multibit Flip-Flops Challenges Built-In Self-Test Solution Using SoC at GHz Functional Equivalence Checking Extraction Flow for 65nm IPs
Session 8 Cadence LBIST for Safety Critical
and Strategies
SoCs

DIG09 (Qualcomm) FED09 (GLOBALFOUNDRIES) PA04 (Texas Instruments) CAV09 (Cadence) CAI09 (Sankalp Semiconductor)
17:30 - 18:00 Parallel Editing in Innovus Physical Aware Test Synthesis Accurate Dynamic Vectorless IR Spectre, Beyond Simulation Intelligent Design Estimator (the
Session 9 Solution for Faster DRC Flow: Challenges and Solutions Analysis with Voltus on a 65nm Performance Floorplanner Tool)
Convergence Low-Power Micro-Controller

18:00 - 18:15 Closing Ceremony

2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.
ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
 View the latest agenda in the mobile app

Conference Agenda: Friday, September 8

TRACK 1 TRACK 2 TRACK 3 TRACK 4 TRACK 5
System Verification: System Verification: System Verification: System Verification: PCB and IC Packaging Design
Time Advanced Verification Performance and Debug Hardware Assisted Formal Room: Grand Victoria A
Methodology Room: Arabica Room: Robusta Room: Boulangerie
Room: Grand Victoria B

08:45 - 09:15 Registration

Welcome
09:15- 09:25
Jaswinder Ahuja, Corporate Vice President and India Managing Director, Cadence

Cadence Keynote
09:25- 09:40
Lip-Bu Tan, President and CEO, Cadence

Cadence Technology Keynote

09:40- 10:10
Oz Levia, Vice President - R&D, System Design & Verification Group, Cadence

Guest Keynote
10:10 -10:40
Dinakar Munagala, Co-Founder and CEO, ThinCi

10:40 - 11:00 Tea Break

11:00- 12:00 Technology Update in Grand Victoria B Technology Update

AVM01 (STMicroelectronics) PER01 (Xilinx) HW01 (NXP) FOR01 (Qualcomm) PCB01 (Sanmina)
Improving Productivity and Verifying DDR4 and LPDDR4 Early, High Performance Software Power Verification Leads to Mastering Advanced-Node
12:00 - 12:30 Efficiency of Functional JEDEC Memory Interfaces Development Using Hybrid Flow Methodology Shift Design Challenges
Session 1 Verification Using the Xcelium
Simulator and MSIE Flow

AVM02 (Xilinx) PER02 (Broadcom) HW02 (Arm) FOR02 (Texas Instruments) PCB02 (Qualcomm)
12:30 - 13:00 Techniques to Reuse Test A Reference Model for PCIe Assertion-Based Verification JasperGold Superlint DFT IBIS Plus Model Generation and
Sequences Across UVM Express Switch Design Using the of Arm 8.2 Cores on Palladium Solution Evaluation Validation Using Sigrity-T2B for
Session 2 Test Benches Purespec VIP for PCIe Platform for System-Level High-Speed I/O Interface
Stress Tests

13:15 - 14:00 Lunch

AVM03 (Ignitarium Technologies) PER03 (STMicroelectronics) HW03 (Broadcom) FOR03 (Analog Devices) PCB03 (VVDN Technologies)
14:00 - 14:30 SV-UVM Methodology for AMS vManager Metric-Driven Signoff Combining UVM-Based A New Use for JasperGold FPV Speed-Up the Work by Allegro
Platform for SoC Verification Acceleration with In-Circuit App: Closing Static Timing Features and Methodologies
Session 3
Emulation for Thorough Analysis
Validation Environment

AVM04 (NVIDIA Graphics) PER04 (MEITY) HW04 (Analog Devices) FOR04 (Samsung) PCB04 (Tejas Networks)
14:30 - 15:00 Experiences with Deploying Unified Approach for Accelerate Embedded Software Fast Forwarding RTL Design 25+ Ways to Increase Your
Cadences VIP Solution for PCIe Performance Evaluation and Development with Palladium Using Formal Verification Design Productivity
Session 4 in UVM-Based PCIe Controller Debug of System on Chip at Early Platform for Tensilica Cores Techniques
Testbench Design Phase

AVM05 (Analog Devices) PER05 (Samsung) HW05 (Texas Instruments) FOR05 (NVIDIA) PCB05 (Molex)
15:00 - 15:30 LDOs and Power Switch DisplayPort IP Verification Accelerating Time to Market of Semi Formal Initial Value Layout Design Automation Using
Verification Using CPF Challenges and Solutions a Robust Functional Safe Device Abstraction and Deep State- SKILL Program
Session 5 for Ultra-High Resolutions with Palladium Platform Space Bug Hunting
(4K) and MST

15:30 - 16:00 Tea Break

AVM06 (NXP) PER06 (SanDisk) HW06 (NXP) FOR06 (Analog Devices) PCB06 (Seagate)
16:00 - 16:30 Assisting Regression of Mixed- Improving Productivity of ATPG- Novel Mechanism to Enable Using Formal to Address Security System-Level Modeling and
Signal Verification for Automotive Based GLS DFT Simulations Software Coverage on Emulator Verification Challenges Correlation for DDRx and ONFI-
Session 6 SoCs: Using SVA and OCEAN NAND Parallel Bus
Scripting

AVM07 (Samsung) PER07 (Juniper Networks) HW07 (Cadence) FOR07 (Qualcomm) PCB07 (Microsemi)
16:30 -17:00 SoC Interconnect Verification Xcelium Simulator: The Next- Virtual Emulation, a Trend that Formal Verification Closure Using Building PCB Designers as
Using Verification Workbench Gen Simulator for Improving Will Replace or Augment In- JasperGold Superlint FPV and First Level of Power Integrity
Session 7 and IP-XACT Flow Productivity of Complex IP Circuit Emulation? Coverage App Engineers Using Sigrity
Verification PowerTree

AVM08 (Qualcomm) PER08 (Samsung) FOR08 (Texas Instruments) PCB08 (Schneider Electric)
17:00 - 17:30 Verification of Multi-Core Sub- Functional Verification Simulation Formal Verification For Analog/ Power Plane Noise Coupling
System Using Perspec System Performance Challenges and Mixed Signal Designs for Noisy Emission Section
Session 8 Verifier with Re-Usable Stimulus Guidelines/Techniques to Get Identification
Breakthrough

AVM09 (Texas Instruments) PER09 (Analog Devices) FOR09 (Texas Instruments) PCB09 (L&T Services)
17:30 - 18:00 Efficient Methodology to FuSa DV: Looking for Holes in an Verifying Large State-Space Power Integrity in High-Speed
Qualify Fault Tolerant Designs ASIL D Safety Concept Design with JasperGold FVP App Digital Designs
Session 9 by Integrating IFSS-IRUN Using
Custom Apps

18:00 - 18:15 Closing Ceremony

2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc.
ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.