Chapter 7

Sequential Circuits: Flip-Flops and Counter

By Taweesak Reungpeerakul

241-208 CH7 1
 Contents

Introduction

Edge-Triggered Flip-Flops (ET-FFs)

FF Operating Characteristics

FF Applications

One-Shots

555 timer

Conclusions
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 Introduction
Well, what u learned before is just one class of digital circuits.

In fact we can classify into two main classes :-

Output can depend on the
past and present inputs/outputs.

Output depends on the present input.

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 Introduction (cont.)
Synchronous VS Asynchronous

All state transitions are State transitions occur independently

controlled by a common clock of any clock

Changes in all variables occur Changes in all variables do not

concurrently necessarily occur concurrently

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 7.1 Latches

A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.

The S-R (Set-Reset) latch is the most basic type. It can be
constructed from NOR gates or NAND gates.

R S Q
Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

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 S-R Latch
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW. 0 R 0
1
Q
Assume the latch is initially RESET Latch
(Q = 0) and the inputs are at their initially
RESET
inactive level (0). To SET the latch 1
0
Q
(Q = 1), a momentary HIGH signal 0 S
is applied to the S input while the R 0 R 1
0
remains LOW. Q
Latch
To RESET the latch (Q = 0), a initially
momentary HIGH signal is SET
0
1
applied to the R input while the S Q
0 S
remains LOW.

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 S-R Latch (cont.)
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH. 1 S 1
0
Q
Assume the latch is initially RESET
Latch
(Q = 0) and the inputs are at their initially
inactive level (1). To SET the latch RESET
(Q = 1), a momentary LOW signal 1
0
1 R Q
is applied to the S input while the R
remains HIGH. 1 S 1
0
Q
To RESET the latch a momentary
Latch
LOW is applied to the R input initially
while S is HIGH.
1 SET
0
Never apply an active set and 1R Q
reset at the same time (invalid).

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 Latch with Enable
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
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 D Latch
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:

D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

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 Truth Table of D Latch
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

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 D Q

Example EN

Q
Determine the Q output for the
D latch, given the inputs shown.

EN

Notice that the Enable is not active during these times, so

the output is latched.

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 7.2 Edge-Triggered Flip-Flops
Circuit type: Synchronous bistable device
Q:What is bistable ?
A: Remain in one of two stable states until it receives a pulse
(logic 1 signal) through one of its inputs, upon which it
switches, or flips, over to the other state.

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 7.2 Edge-Triggered Flip-Flops (cont.)
ET-FF characteristics:
1-bit storage devices
Why? 1) Since outputs can be set to store either 0 or 1,
depending on the inputs
2) outputs retain their prescribed values (bistable
prop.)
FF have 2 complimentary outputs (Q, Q)
Three main FF types: R-S, D-type, J-K
Changes state either at the positive or negative edge of
the clock pulse

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 7.2 Edge-Triggered Flip-Flops (cont.)

The active edge can be positive or negative.

D Q D Q

C C

Dynamic
Q Q
input
indicator
(a) Positive edge-triggered (b) Negative edge-triggered

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments

1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

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 7.2 Edge-Triggered Flip-Flops (cont.)
Q
J 1. More versatile than other FFs.
2. Has 2 inputs (J and K) and 2 outputs
CLK

K Q

Positive ET-J-K
FF symbol

Simplified structure of J-K FF

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 7.2 Edge-Triggered Flip-Flops (cont.)
J Q

CLK

K Q

Positive ET-J-K FF truth table

Inputs Outputs
J K CLK Q Q Comments
How comes ? 0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

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 7.2 Edge-Triggered Flip-Flops (cont.)
Inputs Outputs
Here is one example to test your understanding. J K CLK Q Q Comments

0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

Consider only
positive-edged of
the clock pulse

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 7.2 Edge-Triggered Flip-Flops (cont.)
Inputs Outputs

One more example and try to figure out J K CLK Q Q Comments

No change
by yourself !! 0 0 Q0 Q0
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

Set Toggle Set Latch

CLK

K
Q

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 7.2 Edge-Triggered Flip-Flops (cont.)
Asynchronous Preset and Clear inputs
FF outputs are independent of the clock if either Preset or
Clear is asserted.
PRE

J Q

CLK

K Q

CLR

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 7.2 Edge-Triggered Flip-Flops (cont.)

Check by yourself for this example !

Set Toggle Set Reset Toggle Latch PRE

CLK

J J Q

K Set CLK

PRE Reset
K Q
CLR

Q CLR

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 7.3 FFs Operating Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of
the clock to the 50% level of the output transition.
50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.

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 7.3 FFs Operating Characteristics
(cont.)
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in
the output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.

PRE 50% point CLR 50% point

Q 50% point Q 50% point

tPLH tPHL

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 7.3 FFs Operating Characteristics
(cont.)
Set-up time and hold time are times required before
and after the clock transition that data must be present
to be reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be CLK
present before the clock.
Set-up time, ts

D
Hold time is the minimum
time for the data to remain CLK
after the clock.

Hold time, tH

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 7.3 FFs Operating Characteristics
(cont.)
Some other important characteristics are:-

Maximum clock frequency

Pulse widths

Power dissipation

Speed-power product

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 7.7 Conclusion (cont.)
ET FFs is a synchronous bistable device, whose state
depends on the input only at the triggering transition of a
clock pulse
JK-FFs is mostly used since we can design other FF types
(D,RS) with JK-FF.
Applications of FFs are frequency division, counter, and
storage device.
Monostable and astable are another sequential circuits
which can be implemented with 555 timer.

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