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FSQ0165R PDF
FSQ0165R PDF
September 2007
Features Description
Optimized for Valley Switching (VSC) A Valley Switching Converter generally shows lower EMI
Low EMI through Variable Frequency Control and and higher power conversion efficiency than a
Inherent Frequency Modulation conventional hard-switched converter with a fixed
High-Efficiency through Minimum Voltage Switching switching frequency. The FSQ-series is an integrated
Pulse-Width Modulation (PWM) controller and
Narrow Frequency Variation Range over Wide Load
and Input Voltage Variation SenseFET specifically designed for valley switching
operation with minimal external components. The PWM
Advanced Burst-Mode Operation for Low Standby
controller includes an integrated fixed-frequency
Power Consumption
oscillator, Under-Voltage Lockout, Leading Edge
Pulse-by-Pulse Current Limit
Blanking (LEB), optimized gate driver, internal soft-start,
Various Protection Functions: Overload Protection temperature-compensated precise current sources for
(OLP), Over-Voltage Protection (OVP), Abnormal loop compensation, and self-protection circuitry.
Over-Current Protection (AOCP), Internal Thermal
Shutdown (TSD) Compared with discrete MOSFET and PWM controller
Under-Voltage Lockout (UVLO) with Hysteresis solutions, the FSQ-series reduces total cost, component
count, size and weight; while simultaneously increasing
Internal Start-up Circuit
efficiency, productivity, and system reliability. This device
Internal High-Voltage SenseFET (650V) provides a basic platform that is well suited for cost-
Built-in Soft-Start (15ms) effective designs of valley switching fly-back converters.
Applications
Power Supply for DVP Player and DVD Recorder,
Set-Top Box
Adapter
Auxiliary Power Supply for PC, LCD TV, and PDP TV
FSQ0165RN 8-DIP
-40 to +85C 0.9A 10 10W 15W 9W 13W FSDL0165RN
FSQ0165RL 8-LSOP
Notes:
1. The junction temperature can limit the maximum output power.
2. 230VAC or 100/115VAC with doubler. The maximum power with CCM operation.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50C ambient.
5. Pb-free package per JEDEC J-STD-020B.
VO
AC
IN
Vstr
Drain
PWM
Sync GND
Vfb Vcc
FSQ0365RN Rev.00
+
OSC
0.7V/0.2V
-
+
+
Vref
0.35/0.55
VCC good -
VCC Vref VBurst -
8V/12V
Idelay IFB
Vfb 3R PWM
S Q
3 Gate
Soft- LEB
R R Q driver
Start 200ns
AOCP
1
6V TSD S Q VOCP
VSD GND
(1.1V)
2.5s time R Q
Sync delay
6V
Vovp
VCC good
FSQ0365RN Rev.00
GND D
Vcc 8-DIP D
Vfb V
8-LSOP D
Sync Vstr
FSQ0365RN Rev.01
Pin Definitions
Pin # Name Description
1 GND SenseFET source terminal on primary side and internal control ground.
Positive supply voltage input. Although connected to an auxiliary transformer winding, current
is supplied from pin 5 (Vstr) via an internal switch during startup (see Internal Block Diagram
2 Vcc
Section). It is not until VCC reaches the UVLO upper threshold (12V) that the internal start-up
switch opens and device power is supplied via the auxiliary transformer winding.
The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA
current source connected internally while a capacitor and optocoupler are typically connected
3 Vfb externally. There is a time delay while charging external capacitor Cfb from 3V to 6V using an
internal 5A current source. This time delay prevents false triggering under transient condi-
tions but still allows the protection mechanism to operate under true overload conditions.
This pin is internally connected to the sync-detect comparator for valley switching. Typically the
voltage of the auxiliary winding is used as Sync input voltage and external resistors and capac-
4 Sync
itor are needed to make time delay to match valley point. The threshold of the internal sync
comparator is 0.7V/0.2V.
This pin is connected to the rectified AC line voltage source. At start-up the internal switch sup-
5 Vstr plies internal bias and charges an external storage capacitor placed between the Vcc pin and
ground. Once the Vcc reaches 12V, the internal switch is opened.
The drain pins are designed to connect directly to the primary lead of the transformer and are
6,7,8 Drain capable of switching a maximum of 700V. Minimizing the length of the trace connecting these
pins to the transformer will decrease leakage inductance.
Notes:
6. Repetitive rating: Pulse width limited by maximum junction temperature.
7. L=51mH, starting TJ=25C.
8. Meets JEDEC standards JESD22-A114 and JESD22-A115.
Thermal Impedance
Symbol Parameter Value Unit
8-DIP(9)
JA(10) Junction-to-Ambient Thermal Resistance 80
JC(11) Junction-to-Case Thermal Resistance 20 C/W
JT(12) Junction-to-Top Thermal Resistance 35
Notes:
9. All items are tested with the standards JESD 51-2 and 51-10 (DIP).
10. Free-standing, with no heat-sink, under natural convection.
11. Infinite cooling condition - refer to the SEMI G30-88.
12. Measured on the package top surface.
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 4. Operating Supply Current (IOP) vs. TA Figure 5. UVLO Start Threshold Voltage (VSTART)
vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 6. UVLO Stop Threshold Voltage (VSTOP) Figure 7. Start-up Charging Current (ICH) vs. TA
vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 8. Initial Switching Frequency (fS) vs. TA Figure 9. Maximum On Time (tON.MAX) vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 10. Blanking Time (tB) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA Figure 13. Burst-Mode High Threshold Voltage
(Vburh) vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 14. Burst-Mode Low Threshold Voltage Figure 15. Peak Current Limit (ILIM) vs. TA
(Vburl) vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 16. Sync High Threshold Voltage (VSH) vs. TA Figure 17. Sync Low Threshold Voltage (VSL) vs. TA
1.2 1.2
1.0 1.0
Normalized
Normalized
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-25 0 25 50 75 100 125 -25 0 25 50 75 100 125
Temperature [C] Temperature [C]
Figure 18. Shutdown Feedback Voltage (VSD) vs. TA Figure 19. Over-Voltage Protection (VOP) vs. TA
VCC Vref
Idelay IFB
VDC VO VFB SenseFET
3 OSC
FOD817A
D1 D2
CB 3R
Ca + Gate
VFB* R driver
KA431 -
VCC Vstr
2 5 OLP Rsense
VSD
that the 0.9mA current source flows only through the MOSFET Gate
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
ON ON
feedback voltage (VFB) exceeds 2.5V, the maximum
voltage of the cathode of D2 is clamped at this voltage,
FSQ0365RN Rev.00
thus clamping VFB*. Therefore, the peak value of the
current through the SenseFET is limited. Figure 22. Valley Resonant Switching Waveforms
Gate
triggered during the load transition. To avoid this LEB
R Q driver
200ns
undesired operation, the overload protection circuit is
R
designed to trigger only after a specified time to
determine whether it is a transient situation or a true
Rsense
overload situation. Because of the pulse-by-pulse +
1
current limit capability, the maximum peak current AOCP
-
GND
VOCP
through the Sense FET is limited, and therefore the FSQ0365RN Rev.00
maximum input power is restricted with a given input
Figure 25. Abnormal Over-Current Protection
5. Soft-Start: The FPS has an internal soft-start circuit 7. Switching Frequency Limit: To minimize switching
that increases PWM comparator inverting input voltage loss and EMI (Electromagnetic Interference), the
with the SenseFET current slowly after it starts up. The MOSFET turns on when the drain voltage reaches its
typical soft-start time is 15ms, The pulse width to the minimum value in valley switching operation. However,
power switching device is progressively increased to this causes switching frequency to increases at light load
establish the correct working conditions for transformers, conditions. As the load decreases, the peak drain current
inductors, and capacitors. The voltage on the output diminishes and the switching frequency increases. This
capacitors is progressively increased with the intention of results in severe switching losses at light-load condition,
smoothly establishing the required output voltage. This as well as intermittent switching and audible noise.
mode helps prevent transformer saturation and reduces Because of these problems, the valley switching
stress on the secondary diode during startup. converter topology has limitations in a wide range of
applications.
To overcome this problem, FSQ-series employs a
6. Burst Operation: To minimize power dissipation in frequency-limit function, as shown in Figures 27 and 28.
standby mode, the FPS enters burst-mode operation. As Once the SenseFET is turned on, the next turn-on is
the load decreases, the feedback voltage decreases. As prohibited during the blanking time (tB). After the
shown in Figure 26, the device automatically enters
blanking time, the controller finds the valley within the
burst-mode when the feedback voltage drops below
detection time window (tW) and turns on the MOSFET, as
VBURL (350mV). At this point, switching stops and the
shown in Figures 27 and 28 (Cases A, B, and C). If no
output voltages start to drop at a rate dependent on
valley is found during tW, the internal SenseFET is forced
standby current load. This causes the feedback voltage
to rise. Once it passes VBURH (550mV), switching to turn on at the end of tW (Case D). Therefore, our
resumes. The feedback voltage then falls and the devices have a minimum switching frequency of 55kHz
process repeats. Burst-mode operation alternately and a maximum switching frequency of 67kHz, as shown
enables and disables switching of the power SenseFET, in Figure 28.
thereby reducing switching loss in standby mode.
tB=15s
Burst
mode
ts
IDS IDS
B PO
FSQ0365RN Rev. 00
tB=15s
Figure 28. Switching Frequency Range
ts
IDS IDS
tB=15s
ts
IDS IDS
tB=15s
D
tW=3s
Features
High efficiency ( >77% at universal input)
Low standby mode power consumption (<1W at 230VAC input and 0.5W load)
Reduce EMI noise through Valley Switching operation
Enhanced system reliability through various protection functions
Internal soft-start (15ms)
1. Schematic
C209
47pF
T101
L201
EER2828
16V, 0.3A
11
RT101 1 D201 C202
C201
5D-9 UF4003 470F
470F
R105 C104 C210 35V 35V
R102 2
100k 56k 10nF 47pF
630V L202
C103 D101
R108 1N 4007 12V, 0.4A
33F
62 3
400V 10 D202 C203 C204
2 UF4003 470F 470F
IC101 35V 35V
FSQ0365RN 12
BD101 5 8
1 3 Vstr Drain
Bridge 7
Drain L203
Diode 4 6
Drain C106 C107
Sync 6 5.1V, 1A
100nF 22F R103
3 Vcc 2 SMD 50V 5 C205 C206
4 FB D203
GND 4 1000F 1000F
C102 C105 D102 SB360
1 10V 10V
100nF,275VAC 47nF 1N 4004 R104
50V 12k 5 L204
9
ZD101 3.4V, 1A
1N4746A D204 C207 C208
C110
6.2k 6.2k
1000F
R106 R107
LF101
40mH
8
C302
3.3nF R201
C101 510
100nF R203
275VAC 6.2k
R202
R204 C209
1k
20k 100nF
IC202
TNR FOD817A
10D471K F101
FUSE IC201 R205
KA431 6k
AC IN FSQ0365RN Rev:00
EER2828
12
1 Np/2
Np/2 11
N16V N16V
Np/2 2 10
N12V N12V
3
9 N Na
3.4V
Na 4 8 N5.1V
6mm 3mm
5 N3.4V
7
Np/2
6 N
5.1V
FSQ0365RN Rev: 00
3. Winding Specification
4. Electrical Characteristics
Features
High efficiency ( >70% at universal input)
Low standby mode power consumption (<1W at 230VAC input and 0.5W load)
Reduce EMI noise through Valley Switching operation
Enhanced system reliability through various protection functions
Internal soft-start (15ms)
1. Schematic
C1
4.7nF
L2
660H T1 L1
EE1927
-12V, 0.03A
1N4007
1N4007
RT1 12
1 D1
D3
D2
5D-9 C3 C2
UF4003 100F 100F
CS5 35V 35V
R2 RS5
F1 100k 150k 6.8nF 2 11
FUSE 680V
L3
C6 C7 RS6 DS1 12V, 0.03A
AC IN 10F 10F 200 1N 4007
3 10
400V 400V D4 C4 C5
UF4003 100F 100F
U1 35V 35V
1N4007
1N4007
FSQ311
D6
D5
FB1 11
5 8 Ferritebead
Vstr Drain
7
Drain
4 6 L5
Sync Drain C104* C14 7
100nF 22F R4* 5.1V, 0.9A
SMD 50V 5 D7
3
Vfb Vcc 2 SB360 C12 C11
GND 680F 680F
D8 5 10V 10V
C17 1 ZR1 1N 4004
47nF 1.2k R5
50V 12k 8
6 L6
ZD1 3.3V, 0.9A
1N4746A 9
D9
C18 SB360 C15 C16
6.2k 6.2k
33pF 680F
R7
680F
1N4148
R6
510
R10
6.2k
* : optional components R8
1k R12 C19
8k 68nF
U3
FOD817A
U2 R13
TL431 6k
12 TAPE 4T
1 N-12V
Np/2 Lp/2(0.2) 1
TAPE 2T
11 NVcc 2
Np/2 2 (0.1~0.15) TAPE 2T
6 5
Shield winding TAPE 2T
10 N (0.1~0.15)
1 1
`
12V
3 N12V & N-12V TAPE 1T
(0.1~0.15) 12 11 11 10
9 TAPE 1T
N3.3V N3.3V 8 8 8 9 9 9
(0.2,3parallel)
TAPE 1T
N5V
8 8 8 7 7 7
NVCC 5 8 (0.2,3parallel)
TAPE 1T
Shield winding 1 1
(0.1~0.15) TAPE 2T
6 7 N5V 2
Lp/2(0.2) TAPE 1T
3
Bottom of bobbin
3. Winding Specification
No Pin (sf) Wire Turns Winding Method
Np/2 32 0.2 1 111 Solenoid Winding, 2 Layers
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Shield 1 open 0.1 2 Shield winding
Insulation: Polyester Tape t = 0.025mm, 1 Layer
N5V 78 0.2 3 15 Center Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 1 Layer
N3.3V 98 0.2 3 10 Center Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 1 Layer
N12V 10 11 0.1 1 30 Solenoid Winding
N-12V 11 12 0.1 3 33 Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 1 Layer
Shield 1 open 0.1 2 Shield winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
NVCCV 56 0.1 1 36 Center Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
Np/2 21 0.2 1 111 Solenoid Winding, 2 Layers
Insulation: Polyester Tape t = 0.025mm, 4 Layers
4. Electrical Characteristics
Pin Specification Remarks
Inductance 1-3 2.1mH 10% 66kHz, 1V
Leakage 1-3 100H Max. Short all other pins
9.83
9.00
6.67
6.096
8.255
7.61
0.33 MIN
(0.56) 3.60
3.00 0.356
2.54 0.20
0.56
0.355
1.65 9.957
1.27 7.87
7.62
MKT-MLSOP08ArevA