Hardware Abstraction

VHDL describe a model for a digital hardware device. This model specifies the
external view of the device and one or more internal views.
The internal view of the device specifies the functionality or structure, while
external view specifies the interface of the device through which it communicates
with the other models.
A hardware device may have many device model.
In VHDL ,each device model is treated as a distinct representation of a unique
device, called an entity.

DEVICE Device
model
External View
Digital Model
System

Internal View
 Advantages of HDL
Compact description.
Synchronizing mechanism between concurrent flow
Event scheduling
Easy to edit.
Highly portable.
Various level of abstraction.
Functional simulation early in the design flow.
Rapid prototyping of design.
Design Reuse - Provides Technology independence
Availability of extensive vendor libraries.
Support for hardware concurrency and time frame are two
main features that distinguishes HDLs from other
programming languages.

Limitations of HDL

No support for analog behavior.

Need to learn coding styles that ensures synthesizable results.
 Basic Concepts or Language Elements

Data Objects:-

A data object holds a value of a specified type.There are four Type

of data object in VHDL

1:- Signal

2:- Variable

3:- Constant

4:- File
 Basic Concepts or Language Elements
Data Objects:-
Signal:-

General format of signal

SIGNAL SIGNAL_NAME : SIGNAL_TYPE

[:= INITIAL_VALUE];

The initial value assigned to signal is optional.

Signal clock : bit;

Signal data_bus : bit_vector(7 downto 0);
Signal signal_delay :time:= 10 ns;
 Basic Concepts or Language Elements

ENTITY SIGNAL_ EXAMPLE IS

PORT ( A, B, C, D : IN BIT;
E : OUT BIT);
END SIGNAL_EXAMPLE;

ARCHITECTURE BEHV_SIGNAL OF SIGNAL_EXAMPLE

IS
SIGNAL S, T : BIT;
BEGIN
PROCESS (A, B, C, D, S, T)
BEGIN
S <= A AND B;
T <= C AND D;
E <= S OR T;
END PROCESS;
END BEHV_SIGNAL;
 Basic Concepts or Language Elements

Data Object
Variable:-

General format of variable declaration is

VARIABLE VARIABLE_NAME : VARIABLE_TYPE

[ := VALUE];

The initial value assigned to variable is optional.

Variable sum : integer range 0 to 100:= 10;

Variable C1,C2 : bit;
 Basic Concepts or Language Elements
Data Object
Constant:-
The general format of constant declaration is :

CONSTANT CONSTANT_NAME : CONSTANT_TYPE

[ := INITIAL_VALUE];

CONSTANT ZERO : BIT_VECTOR (0 TO 3): = 0000;

Constant bus_width : Integer := 8;
Constant rise_time : Time :=10 ns;

Value once assigned to a constant can not be changed.

While declaring a constant the assigning of value is optional.
 Basic Concepts or Language Elements
Data Object
File :-
The syntax of a file declaration is
File file_names : file_type_name [[open mode] is string
expression];

Example:- Type std_logic_file is file of std_logic_vector;

File pat1,pat2 : std_logic_file;

File stimulus : TEXT open Read_mode is /usr/home/add.sti;

An object belonging to the file class contain a sequence of value. Value can be
read or written to the file using read procedures and write procedures,
respectively.
Basic Concepts or Language Elements

Data Type:-
1:- Scalar types

(i) Integer

(ii) Enumeration

(iii) Physical*

(iv) floating point*

2:- Composite Types

(i) Array

(ii) Record

The value set is defined in a model using a type declaration along with
the object kind.
 Basic Concepts or Language Elements
Scalar Types:-

The value belonging to these types are ordered, that is, relational
operators can be used on these values.

Example:- Bit is a scalar type, and the expression 0 < 1 is valid and has the
value
True.

Integer and Enumeration types are called discrete types because these type have
discrete value associated with them.

Every value belonging to an enumeration type, integer type, or a physical type has
a position number associated with it.
 Basic Concepts or Language Elements

Array in turn can be of two different types :

 Basic Concepts or Language Elements
Array type
Constrained type
For these types, range or size is completely specified when they
are declared

TYPE NEW_INTEGER IS ARRAY (0 TO 7) OF INTEGER;

--RANGE 0 TO 7 IS CLEARLY SPECIFIED

Unconstrained type
Array types whose range is not specified when declared

TYPE BIT_VECTOR IS ( NATURAL RANGE < >) OF BIT;

Unconstrained array types find good use in subprograms.

 Basic Concepts or Language Elements
Data Types
Record type :
An object of record type is composed of elements of same or different types
Example:

type pin_type is integer range 0 to 10;

type module is
record
Size : integer range 20 to 100;
critical_dly : time;
no_inputs : pin_type;
no_outputs : pin_type;
end record;
variable nand_comp : module;
nand_comp :=(50, 20 ns, 3, 2);
 Basic Concepts or Language Elements

Operators supported by VHDL

Supports following operators:

1. Logical operators
- AND
- OR operate on bit but
- NAND can be overloaded
- NOR for operations
- XOR on bit_vector

.
 Basic Concepts or Language Elements

2. Relational operators

Compare the two values of the same base and return a Boolean value
- = (Equal)
- =/ (Not equal)
- > (Greater than)
- >= (Greater than equal to)
- < ( Less than)
- <= (Less than equal to)
 Basic Concepts or Language Elements

3. Adding operators
- +
- -
- &
Operators + and -are predefined for integer operands can be
overloaded for operation on data of the type bit_vector.

Concatenation operator & is predefined for one-dimensional

array.
SIGNAL A : BIT_VECTOR (0 TO 3);
SIGNAL B : BIT;
SIGNAL C : BIT_VECTOR(0 TO 4);
C<= B & A;
--IF A="0000" AND B = '1' THEN C ="10000"
 Basic Concepts or Language Elements

4. Multiplying operators
- * (Multiply)
- / (Divide)
- Rem
- Mod

5. Miscellaneous operators
- ** (Exponent)
- Abs (absolute)
- Not
 Basic Concepts or Language Elements

Operators : Classified Categories

i. Arithmetic operators
ii. Relational operators
iii. Equality operators
iv. Logical operators
v. Bit wise operators
vi. Reduction operators
vii. Shift operators
viii.Conditional operators
ix. Concatenation operators
x. Logical Comparators
 Design Units of VHDL

1. Entity declaration

3. Architecture Body

5. Configuration Declaration

7. Package Declaration

9. Package Body
 Entity Declaration

Entity declaration describes the external view of the entity ;

for example, the input and output signal names.

Syntax for an entity declaration:

entity entity_name is
[generic (list-of-generics-and-their-types);]
[port (list-of-interface-port-names-and-their-types);]
end [entity] entity-name;
 Architecture Body
Architecture body: describes the function of a design.

Architecture body gives the functional behavior of the entity i.e. how its
inputs and outputs are related.
Architecture is the textual representation of the graphical schematic.

Syntax for an architecture body

architecture architecture_name of entity_ name is

end architecture_name;
 Architecture Body

Statements in architecture body :-

The internal details of an entity are specified by an architecture

body using any of the following modeling styles:

Structural :- As a set of interconnected components.

Dataflow :- As a set of concurrent assignment statement.
Behavior :- As a set of sequential assignment statement.
Mixed :- As any combination of the above three .
 Configuration Declaration

A configuration declaration is used to select one of the possibly many

architecture bodies that an entity may have , and to bind components,
used to represent structure in that architecture body.

Syntax for a configuration declaration

Library library_name;
Configuration Configuration_name of entity_name is
For architecture_name
Use entity library_name. entity_name(architecture_name);
End for;
End Configuration_name
 Package Declaration

A package declaration is used to store a set of common declarations,

such as components, types, procedures, and functions. These
declarations can then be imported into other design units using a use
clause.

Syntax for a package declaration :-

Package package_name is

[type type_name is ( );]

[constant constant_name:constant_type[:=initial value];]

End package_name;
 Package Body
A package body is used to store the definitions of functions and procedures
that were declared in the corresponding package declarations.

Syntax for a package body :-

Package body package_name is

[constant constant_name:constant_type[:=initial value];]
[type type_name is ( );]
[Function function_name --function body.
( )] is
begin
[ --function description
];
End function_name;
End package_name;
 Entities and Architecture in VHDL
Example

entity eqcomp4 is
Port Declaration
port (a, b : in bit_vector(3 downto 0);
equals: out bit );
end eqcomp4;
architecture dataflow of eqcomp4 is
begin
equals <=1 when (a=b) else 0;
end dataflow;
Entities and Architecture in VHDL
Entities and Architecture in VHDL

Declarations in entity
The declarations allowed in entity declaration region include
Type declaration
subtype declaration
signal declaration
constant declaration
alias declaration
use clause
subprogram declaration
subprogram body
Entities and Architecture in VHDL

Some other declarations in entity

Some other declarations allowed in entity declaration region
include
ATTRIBUTE DECLARATION
ATTRIBUTE SPECIFICATION
DISCONNECTION SPECIFICATION

Declarations made in the entity declaration area are visible to the

architecture(s) of the entity.

 Entities and Architecture in VHDL

ARCHITECTURE FLOW_ONE OF FULL_ADDER IS

BEGIN
SUM <= ((NOT (A) AND (NOT (B) AND C_IN)
OR
((NOT (A) AND (B) AND (NOT (C_IN)))

OR
((A) AND (NOT (B)) AND (NOT (C_IN)))
OR
((A) AND (B) AND (C_IN));
CARRY <= ((NOT (A)) AND (B) AND (C_IN))
OR
((A) AND (NOT (B)) AND (C_IN))
OR
((A) AND (B) AND (NOT (C_IN)))
OR
((A) AND (B) AND (C_IN));
END FLOW_ONE;
Examples

AND Gate > logic equation

entity and1 is
port (a,b,c : in std_logic; z :out std_logic);
end and1;
Architecture dataflow of and1 is
begin
z <= a and b and c;
End dataflow;
Examples

2. Full adder
-entity full_adder is
Port ( x : in istd_logc; --input x
y : in std_logic; --input y
cin: in std_logic;-- input carry
s : out std_logic; --output sum
cout : out std_logic); --output carry
end full_adder;

architecture dataflow of full_adder is

begin
s<= (x xor y) xor cin; --summing of two bit in carry also included
cout<=(x and y)or(x and cin)or(y and cin); --output carry
end dataflow;
3. MUX_4_1 >
entity mux41 is
Port ( i0,i1,i2,i3,s0,s1 : in std_logic;
y : out std_logic);-- output
end mux41;
architecture dataflow of mux41 is
begin
Y <= (i0 and (not s0)and(not s1)) or (i1 and (not s0)and s1)or
(i2 and s0 and(not s1))or(i3 and s0 and s1);
end dataflow;