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Orcad Fpga Ds
Orcad Fpga Ds
The Cadence OrCAD FPGA System Planner addresses the challenges that engineers encounter
when designing large-pin-count FPGAs on the PCB boardwhich includes creating the initial pin
assignment, integrating with the schematic, and ensuring that the device is routable on the board.
By replacing manual, error-prone processes with automatic pin assignment synthesis, this unique
placement-aware solution eliminates unnecessary physical design iterations while shortening the
time required to create optimum pin assignment.
Designing large-pin-count
FPGAs on PCBs
Integrating todays FPGAswith Differential
their many different types of assign- User IO
ment rules and user-configurable
pinson PCBs is time consuming and
extends design cycles. Often the pin
assignment for these FPGAs is done Configurable
manually at a pin-by-pin level in an
environment that is unaware of the
placement of critical PCB components
that are connected to FPGAs. Without Clock
Capable
understanding the impact to PCB Power
Benefits Figure 2: Placement/Floorplan view of the OrCAD FPGA System Planner provides users relative
placement of critical components for optimum pin assignment synthesis
Scalable, cost-effective FPGA-PCB
co-design solution from OrCAD to all, there is no online rules-checking to thereby extending the time it takes to
Allegro GXL ensure that the right pin types are being integrate todays complex, large-pin-
used for the signals that are assigned to count FPGAs on a PCB.
Shortens time for optimum initial pin the FPGA pins. As a result, users have
assignment, accelerating PCB design Specifying Design Intent
to make several iterations between the
schedules spreadsheet-based tools and the tools The OrCAD FPGA System Planner comes
from FPGA vendors. Often this adds an with an FPGA device library to help with
Accelerates integration of FPGAs
increased number of iterations between selection of devices to be placed. It uses
with OrCAD PCB design creation
the PCB layout designer who cannot OrCAD PCB Editor footprints for the
environments
route the signals from FPGA pins on floorplan view and allows users to quickly
Eliminates unnecessary, frustrating available layers and the FPGA designer create relative placement of the FPGA
design iterations during the PCB layout who has to accept paper-based or verbal system components.
process pin-assignment suggestions from the
PCB layout designer. Once a change is The OrCAD FPGA System Planner allows
Eliminates unnecessary physical users to specify connectivity between
made to the pin assignment by the FPGA
prototype iterations due to FPGA pin components within the FPGA sub-system
designer, the pin assignment change
assignment errors at a higher level through interface defini-
has to be made in the schematic design
Reduces PCB layer count through by the hardware designer. Such itera- tions. Users can create interfaces such as
placement aware pin assignment and tions add several days if not weeks to the DDR2, DDR3, and PCI Express, and use
optimization design cycle and possibly a great deal of these to specify connectivity between an
frustration for the team members. Since FPGA and a memory DIMM module or
Features this is a manual process, mistakes that are between two FPGAs. The OrCAD FPGA
not detected can also cause expensive System Planner understands differential
OrCAD FPGA System Planner physical prototype iterations. signals, and power signals, as well as
Technology clock signals.
While it may help to automate the
An FPGA system is defined as a subset of synchronization of changes made to the FPGA Device Rules
the PCB design that includes one or more pin assignment by the FPGA designer, The OrCAD FPGA System Planner comes
FPGA and non-FPGA components that are hardware designer, or PCB layout with a library of device-accurate FPGA
connected to FPGAs. designer, it doesnt reduce the root cause models that incorporate pin assignment
Traditional approaches to pin assignment of these iterations. Pin assignment that rules and electrical rules specified by
are typically manual and often based is not guided by all three aspectsFPGA FPGA device vendors. These FPGA models
on a spreadsheet. Tools such as these resource availability, FPGA vendor pin are used by the synthesis engine to ensure
require users to do pin assignment with- assignment rules, and routability of FPGA that the vendor-defined electrical usage
out taking into consideration the place- pins on a PCBrequires many iterations rules of the FPGAs are strictly adhered to.
ment of other components and routability at the tail end of the design process, These rules dictate such things as clock
of the interfaces and signals. Above
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Cadence OrCAD FPGA System Planner
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Cadence OrCAD FPGA System Planner
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
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