Microprocessors and its Applications A-% Appendix - A Timing DAD rp This instruction adds 16-bit data from specified register pair or stack pointer in the contents of HL register pair and stores the result in the HL register pair. This instructior requires three machine cycles. [ OPCOODE FETCH ‘BUS IDLE BUS IDLE ele De Tee Pe ee De O/T 8, Sitivan a= Yormaaa-16 4 wt mm ri NTA DAD & 09 DAD mp F DAD D 19 OAD sp] ® DAD _H_ 29 Table AS Fig, A.35 1) Opcode fetch : Program counter places the memory address on low-order anc high-order address bus. This machine cycle is required for reading the opcode of DAL (eg. 09 for DAD B) into the microprocessor and decode it. 2) and 3) Bus Idle These machine cycles are required to do the internal operation ie. to perform 16-bi — addition. During these machine cycles buses are not in use.Timing diagram 11 : DCX rp and INX rp These instructions decrement/increment the contents of register pair (rp) specified within the register by one and store result in the same register pair. It requires only opcode fetch machine cycle. In this cycle, program counter gives address on low order and high order address bus. The opcode of DCX rp (e.g. 0B of DCX B) is read into the microprocessor and it decodes it. This machine cycle requires 6 T-states. Fig. A.26 gives the timing diagram of DCX rp. The instruction INX rp also has same timing diagram, the only difference is the opcode. Fig, A.36Microprocessors and its Applications _A- 43 Appendix -A Timing diagram 18 : IMP address This instruction loads the program counter with the address given within the instruction and resumes the program execution from this location. It requires three machine cycles as explained below. ‘OPCODE FETCH MEMORY READ | MEMORY READ 2 [ts | % | | m | | | me | ts MP J conditions (when condition is ‘vaiid) * for instruction JNZ addy, it Zero Nag is not set at me tne of exe- ‘ution of instruction condition is valid. Table A141 Fig. A.43 1) Opeode fetch : Program counter places address on low order and high order address bus. The opcode of JMP (C3H) is read into the microprocessor from this address and is decoded. Program counter is incremented by one. 2) Memory read : Program counter gives address on low order and high order address bus. The data at this addressed memory location is read into the microprocessor. This data is nothing but the low order byte of the address specified within the instruction. Program counter is incremented by ane.Microprocessors and its Applications A-vH Appendix -A MEMORY READ 1011 #0,3, «0. S.= 1010/7 = 0, $= 0.3, = 1¥ 101M <0, S,*0.5, 27 LDA Aeros 10) =0,5,41,5,41 [i [2 [m [uf [ef [4 Te [ts [1 | OPCODE FETCH MEMORY READ g % L n & is 2 Fig. A.32 2) Memory read : Program counter gives address on low-order and high-order address bus. In this machine cycle, the low-order byte of the address specified within the instruction is read into the microprocessor from the addressed memory location. Program counter is incremented by one. 3) Memory read : Program counter gives the address on low-order and high-order address bus. In this machine cycle, the high order byte of the address specified within the instruction is read into the microprocessor from the addressed memory location. Program counter is incremented by one,Microprocessors and its Applications A-33 Appendix - A Timing diagram 9 : LDAX rp This instruction loads A register with the contents of memory location whose address is specified by register pair (BC or DE). It requires the following machine cycles. 1) Opcode fetch : Program counter places the memory address on low-order and high-order address bus. This machine cycle is required for reading the opcode of LDAX rp (eg. 0A for LDAX B) into the microprocessor and decode it. 2) Memory read ; This machine cycle is required for reading the data into the accumulator, The address at which the data is stored is obtained from register pair specified within the instruction. In this machine cycle higher order register contents are kept on higher-order address bus and lower order register contents are kept on Jower-order address bus. The data is read into the microprocessor (register A) from the addressed memory location. Fig. A.34 gives the timing diagram. [ff [™ [% [ % [7 | Fig. A.34LHLD 2500 H This is a three-byte instruction so it requires 3 machine cycles to fetch the instruction, These cycles are opcode fetch, operand read and operand read. The LILD instruction loads the contents of memory 25001 and 250111 into L and If registers. To load these memory contents into HL 2 more memory read cycles are required, So, in all, 5 machine cycles are required, Opcode fetch: To take opcode of LHLD instruction, address is given by PC and then PC is incremented by |. T;- and T,-states are not required so opcode fetch is of T,- to T,-states only, Operand fetch: This cycle is performed to take lower order address, PC gives address for this and then PC is incremented by 1. The lower address is stored in temporary register W. Operand fetch: This cycle is performed to take higher order address, PC gives addres: for this and then PC is incremented by 1. The higher order address is stored in temporary register Z. Memory read: This cycle is performed to take data from memory, This data will be stored in L register. Address for this is given by instruction, i.c., above 2 memory reads has read the address with instruction and stored in temporary registers W and Z, ‘The WZ will give the address; address will be incremented by 1Microprocessors & Microcontrollers-| 5 - 55 8086 Instruction Timing Diagrams Pee Tt Rls) Fig. 5.54 Timing diagram 30 : MOV M, r Fig. 5.55 shows the timing diagram of MOV M, r instruction. This instruction copies the contents from the specified register into the memory location pointed by HL register pair. This instruction requires two machine cycles. MEMORY WRITE [tT % [i [% [ % [ % Ts | om s,s, onivasniast Yomivaarran) “Fig. 5.55Microprocessors and its Applications = A- 24 Appendix - A A6 Timing Diagrams for 8085 Instructions In this section timing diagrams for all 8085 instructions are explained in detail. In 8085 many instructions require same machine cycles. Those instructions are grouped and represented with a single timing diagram with different opcodes shown in table along with timing diagram. Timing diagram 1 : MVI A, data ..... MVI L, data These instructions directly load a specified register with a data byte specified within the instruction. They require the following machine cycles. 1) Opcode fetch : Program counter gives the memory address on low-order and high order address bus. This machine cycle is required for reading the opcode into the microprocessor and decode it. Program counter is incremented by one. 2) Memory read : This machine cycle reads the data from addressed memory location into specified register of the microprocessor. Fig, A.26 shows the timings required for different signals. Table A2 gives the instructions for which the timing diagrams are same. Only difference is in opcode. e seueeayensaa ZMONe> febeteeseeeeee BMSREKASLAASLS 3 g & 10/1 8,5) iGTiming diagram 17 : SHLD address Fig. A.42 gives the timing diagram of SHLD address instruction. This instruction stores the contents of L register in the memozy location given within the instruction and contents of H register at address next to it. It requires the following five machine cycles. 1) Opeode fetch : Program counter places address on low order and high order address bus. Microprocessor reads the opcode of SHLD (22H) from this memory location and decodes it, Program counter is incremented by one. 2) Memory read : Program counter gives address on low order and high order address bus. Microprocessor reads data from the addressed memory location, This data is the low order byte of the address specified within the instruction. Program counter is incremented by one. 3) Memory read : Program counter gives address on low order and high order address bus. Microprocessor reads data from the addressed memory location. This data is the high order byte of the address specified within the instruction. 4) Memory write : The data read in the previous two memory read cycles is placed on the address bus. Microprocessor writes the contents of L register at this memory address. This memory address is incremented by one. 5) Memory write : Now the incremented address is present on the address bus. Microprocessor writes the contents of H register at this memory address.‘OPCODE FETCH |_MEMORY READ | MEMORY READ MEMORY WRITE | MEMORY WRITE we SuoHedddy $31 pue ss0sse20;dos09y v-xipueddyTiming diagram 15 : SPHL This instruction copies the contents of HL register pair into the stack pointer. It requires only opcode fetch machine cycle. In this, program counter gives address on low order and high order address bus. Microprocessor reads the opcode of SPHL (F9H) from this addressed memory location and decodes it. Program counter is incremented by one, This machine cycle requires 6 T-states, Fig. A.40 gives the timing diagram of SPHL. mas, (_emnana Fig. A.40 Timing diagram 16 : LHLD address Fig. AAl gives the timing diagram of LHLD address instruction. This instruction loads L register with the contents of memory location given within the instruction and loads H register with the contents of memory location at address next to it. It requires the following five machine cycles.f ‘OPCODE FETCH MEMORY READ | MEMORY READ | MEMORY WRITE ele [ale tutus ls[e—sts[e[s ‘suonediiddy sy pue siossacoidoi9iy o-v‘Meany Gagan 8 : STAX rp This instruction stores the contents of A register in memory whose address is specified by register pair (BC or DE). It requires the following machine cycles : 1) Opcode fetch : Program counter places the memory address on low-order and high-order address bus. This machine cycle is required for reading the opcode of STAX rp (eg. 02H for STAX B) into the microprocessor and decode it. 2) Memory write : Higher-order address is obtained from higher-order register and lower address is obtained from lower-order register of the specified register pair. The contents of the accumulator are stored into the addressed memory location. Thus memory write machine cycle is required for writing the data from the microprocessor (A register) to the addressed memory location. Fig. 5.33 gives the timing diagram for STAX rp. SPCODE FETE % Tn Teln| Fig. 5.33