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SEPIC PFC Rectifiers
SEPIC PFC Rectifiers
Capacitor
Voltage-Doubler SEPIC PFC Rectifiers
Paulo J. S. Costa, Carlos H. Illa Font, Member, IEEE, Telles B. Lazzarin, Member, IEEE
C. H. Illa Font is with the Department of Electronics Engineering, Federal
Abstract In this paper, the switched-capacitor concept is University of Technology Paran, Ponta Grossa, Brazil (e-mail:
illafont@utfpr.edu.br).
extended to the voltage-doubler DCM SEPIC rectifier. As a
result, a set of single-phase hybrid SEPIC PFC rectifiers able to proposed in [5]-[8]. These topologies are referred to as voltage-
provide lower voltage stress on the semiconductors and/or higher doubler rectifiers and provide, when compared to the
static gain, which can be easily increased with additional conventional Boost rectifier, gains in relation to cost and
switched-capacitor cells, is proposed. Hence, these rectifiers efficiency and supply twice the output voltage (hence the term
could be employed in applications that require higher output voltage-doubler) or a lower voltage stress on the
voltage. In addition, the converters provide a high power factor semiconductors.
and a reduced total harmonic distortion in the input current. The Other examples of PFC rectifiers available for application with
topology employs a three-state switch, and three different higher output voltage are the voltage-doubler SEPIC converters
implementations are described, two being bridgeless versions,
addressed in [6], [9] and [10]. These converters operate in
which can provide gains in relation to efficiency. The structures
and the topological states, a theoretical analysis in steady state, a
discontinuous conduction mode (DCM), because in this
dynamic model for control and a design example are reported operation mode the input current naturally has the same shape (if
herein. Furthermore, a prototype with specifications of 1000 W the high-frequency ripple of this current is neglected) and phase
output power, 220 V input voltage, 800 V output voltage and 50 of the input voltage [9], [11], [14]. Hence, the rectifier does not
kHz switching frequency was designed in order to verify the require a current control loop, which simplifies its control system.
theoretical analysis. Furthermore, in the case of these rectifiers, the input current does
not have the third harmonic, do not need additional bulk filters
Index Terms Voltage-doubler DCM SEPIC, Single-phase [10], [13], [14], and impose reduced voltage stress on the
rectifier, Switched capacitor, Bridgeless, High power factor. semiconductors.
On the other hand, recent publications describe a new class of
PFC rectifiers, referred to as hybrid (pulse-width-modulated +
I. INTRODUCTION switched capacitor) rectifiers [3]. This class integrates
conventional rectifiers with the switched-capacitor converters
I high dc output voltage for use in distributed generation, n
recent years, the market demand for power supplies with (SCC), which are able to divide or multiply a voltage without
renewable energy, energy storage, dc-dc smart grids, electrical increasing the voltage stress across the semiconductors [3], [15]-
vehicles, UPS, X-ray systems, and motor drivers has increased [18]. Hence, this new class of PFC rectifiers can be employed in
[1]-[3]. In these applications the power supply can be used to applications that require higher dc output voltage (above 400 V).
directly feed a load or as an input stage of another power Although the concept of hybrid rectifiers is recent, it has
converter [3]. In both cases, the system is commonly fed by an ac already provided opportunities for new lines of research [3], [16],
grid. Hence, a converter with power factor correction (PFC) is [19], [20]. In this context, based on the voltage-doubler SEPIC
required to provide a high power factor and reduce the total rectifier in [10], multiplier SEPIC dc-dc converter in [15],
harmonic distortion in accordance with the regulations and switched capacitor (SC) cell in [17], hybrid rectifiers in [3], [16],
standards, such as IEC 6100-3-2 [4]. [19], [20] and studies described in [9], [11], [12] and [21]-[27],
Due to the current source characteristic at the input, structures this paper proposes a set of single-phase hybrid voltage-doubler
derived from Boost converters are normally employed in stages SEPIC rectifiers. These rectifiers provide a high power factor,
with power factor correction. Some Boost rectifiers suitable for reduced total harmonic distortion (THD), reduced voltage stress
applications with high output voltage are on the semiconductors and higher dc output voltage values
(above 800 V).
The Boost converters integrated to SC cells approached in [3]
This work was supported by CAPES Brazilian Federal Agency for and [16], in contrast to the proposed rectifiers in this paper,
Support and Evaluation of Graduate Education within the Ministry of operate in continuous conduction mode (CCM). Therefore, these
Education of Brazil, Federal University of Santa Catarina and Power structures require a control loop to regulate the input current,
Electronics Institute (INEP).
P. J. S. Costa and T. B. Lazzarin are with the Department of Electrical
which makes the control system of the converter more complex.
Engineering, Federal University of Santa Catarina, Florianopolis, Brazil Furthermore, the Boost rectifiers operate with variable duty
(email: paulojunior@inep.ufsc.br; telles@inep.ufsc.br). cycle, which increases the losses in the SC. The converters
addressed in [15] and [17]-[18] use the conventional ladder SC
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cell in dc-dc and ac-ac conversion and the same cells are applied
in [3] and [16]. The conventional ladder SC cell does not work in
the SEPIC rectifier. Hence, in [19-20] was proposed a modified
ladder SC cell that allows the integration between SCC and
classical SEPIC rectifier. Despite employing an additional
semiconductor, this modified cell allows the rectifier to work
properly and it preserves the high quality of the input current,
which is an important characteristic of the SEPIC rectifiers that
operate in DCM. However, only a partial analysis of the
switched-capacitor integrated to the classical SEPIC rectifier is
approached in [19] and [20].
The proposed converters provide an increase of the static gain
and a reduction in the voltage stress on the semiconductors in
relation to the rectifier addressed in [10], but the structures use
more elements. With regard to the converters described in [19]
and [20], the proposed rectifiers also employed a greater number
of components. Nevertheless, these rectifiers provide, for a same
number of switched capacitor cells, a reduction in the voltage
stress on the semiconductors and are able to process twice more
power, because these converters work as two half-wave rectifiers,
one for each half-line cycle. Due to the characteristic of operation
in half-line cycle, the current and voltage stress are divided
among the elements of the circuit and, consequently, the
proposed rectifiers can process higher power levels.
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the output voltage. The first four states are described below in
detail.
Stage 1 (Fig. 3 (a)): This stage starts when the switch S1 is
turned on. The diodes D1, De1 and De2 are forward-biased while
all other diodes are reversed-biased. The elements S1,
De1 and De2 connect the capacitors Co1 and CS1 in parallel.
However, the charge current of CS1 does not flow through Ci1 due
to the modified switched-capacitor cell. The switched capacitor
CS1 is charged by Co1 from S1, De1 and De2 and it presents voltage
equal to vCo1 which, in turn, is equivalent to vo/(2 + n). The
current in the inductors Li and Lo1 increases linearly in agreement
with the vg/Li and vg/Lo1 ratios, respectively. The load Ro is fed by
the capacitors Co1, Co2, Co3 and Co4.
Stage 2 (Fig. 3 (a)): This state is initiated when the switch S1
is turned off. Diodes D1, Do1, Do2 and De3 are forwardbiased and
all other diodes are blocked. The elements Do2, Do1 and De3
connect CS1 and Co4 in parallel. Hence, the voltages on theses
capacitors are equal to Vo/(2 + n). The current that flows through
these elements is provided by inductors Li and Lo1. The current in
the inductors Li and Lo1 decreases accordingly with relations
[Vo/(2 + n)]/Li and [Vo/(2 + n)]/Lo1, respectively. The load Ro
and output capacitors are supplied by energy previously stored in Fig. 2. The proposed single-phase hybrid voltage-doubler SEPIC rectifier with
Li and Lo1 in the first stage. two active switches (2S-bridgeless version) and with n = 2.
Stage 3 (Fig. 3 (c)): During this stage the switch S1 remains
turned off and the diodes D1, Do2 and De3 are forward-biased. III. DESIGN EQUATIONS
Diode Do1 and all other semiconductors are blocked. The A. Voltage-Doubler SEPIC Converter Cell Design
capacitors CS1 and Co4 remain connected in parallel through the
The main design equations for the voltage-doubler SEPIC
diodes Do2, Do1 and De3. The energy stored in the inductors Li and
converter cell are reported in Table I. Details of the determination
Lo1 flows through Do2, CS1 and De3 to the load Ro and the output
of these numerical expressions can be found in [10].
capacitors.
Stage 4 (Fig. 3 (d)): This subinterval is the traditional B. Switched-Capacitor Cell Design
discontinuous stage of the SEPIC converter. During this stage all
Fig. 7 (a) highlights the ladder-type switched-capacitor cells
of the semiconductors are turned off and the current in the
integrated with the voltage-doubler SEPIC rectifier. These cells
inductors Li and Lo1 is constant. Hence, the voltage across these
can be represented by an equivalent circuit, such as that shown in
inductors is zero. The voltage on the capacitors CS1, CS2 Co1, Co2,
Fig. 7 (b), where Ron-c is the total conduction resistance of the
Co3 and Co4 is equal to Vo/(2 + n). The load Ro is fed by the output
switched capacitor (semiconductors resistances (Ron) plus the
capacitors.
capacitor resistances (Rce)).
B. Main Ideal Waveforms The switched-capacitor cell shown in Fig. 7 (b) can be
represented by an equivalent resistance (Req) as shown in Fig. 7
The main theoretical waveforms of the proposed converter, for
(c). The value of Req is defined by the expression (1) [23] and it
the case where the input voltage achieves the highest level, which
is a function of the system switching frequency (fs), duty cycle
is denominated as (Vp), are shown in Fig. 4, Fig. 5 and Fig. 6. The
waveforms for one switching period are shown in Fig. 4 and Fig. (D) and time constant defined in (2).
5. These figures show the current and voltage in the inductors Li,
Lo1 and Lo2, the current in the capacitors Ci1, Ci2, CS1 and CS2, and
the current and voltage on the semiconductors S1, S2 and Do1, (1)
Do2, Do3 and Do4. Fig. 6 shows, for one grid period, the input Req = D 1
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( )c ( )d
Fig. 3.
Operation stages of the rectifier 2S with n = 2 for positive cycle of voltage grid: (a) first stage, (b) second stage and (c) third stage, and (d) fourth stage.
The Pc boundaries are shown in Fig. 8 (a). The border with Tc
charge (Pc) and No charge (Nc) [22]. For each mode the behavior presents Req = 14.4 Ron-c and fs = 0.07. On the other hand, the
of the current in the capacitor differs, as is demonstrated in Fig. border with Nc occurs at Req = 4.44 Ron-c and fs = 1.306. Thus,
8 (b), (c) and (d). there is a considerable difference between these limits. Fig. 8 (a)
Based on the curve of Req (Fig. 8 (a)) and the current behavior also defines an internal operation point, where fs is equal to 0.5.
in each operating mode (Fig. 8 (b), (c) and (d)) it can be This point has an equivalent resistance of 1.08 pu regarding the
concluded that the Tc mode presents greater loss due to the higher minimal resistance (when fs tends to infinity Req reaches its
peak current; however, it requires a lower capacitance value lowest value of 4.4, considering D = 0.35). After fs = 0.5, if the
(considering constant switching frequency). The Nc mode fs value is increased by a factor of two, the Req value reduces by
presents less loss; however, it requires higher capacitance values. only 6%. This analysis suggests the use of an fs value equal to
Therefore, in relation to losses and volume, Pc is the best or close to 0.5, because fs > 0.5 increases the volume of the CS
operating mode.
or the switching frequency; however, it
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Stages Stages
T
S De6 are described, respectively, in
Fig. 4. Ideal waveforms (currents) for a switching period of the rectifier 2S with n
= 2.
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switchedcapacitor cell employed in the proposed rectifier and (c) equivalent
resistance of the switched-capacitor cells.
(4 DV Vo ) ,
2 2
DVIC
p S 1 max IC S 1 min p
(5)
IC S 1 _ RMS = C S 2 _ RMS =
2 Vo
IC o 3 _ RMS = IC o 4 _ RMS =
(6)
( )+
2
( IC S 1max IR o ) Vo
2 2 3
2 DV p R o Vo
2
VR
oo
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n is an even number which is greater than or equal to two.
Vp: peak value of the input voltage; Vo: average value of the output voltage;
Po: output power; Ro: load resistance; Req: equivalent resistance of the
C. Generalization of Switched-Capacitor Cell Number
switched capacitor cell; L : equivalent inductance; i : ripple current of the
eq Li
The proposed converter is able to provide high output voltage,
inductor Li; VCi1: ripple voltage of the capacitor Ci1; fs: switching frequency; since it can be generalized by adding switchedcapacitor cells, in
D: duty cycle and thut: hold-up-time, ICS1max: maximum current in CS1; ICS1min: a modular way, as demonstrated in Fig. 1. Thus, the number of
minimum current in CS1. components in the multiplication stage, the average values for the
output voltage and the voltage stress on the elements are directly
and proportional to the number of switched-capacitor cells employed.
A generalization in relation to the number of switched-capacitor
Req cells (n) can be seen in Table III.
20 Ronc
[.007144
, .]
IV. CONTROL AND DYNAMIC MODEL
A. Dynamic Model for Control
12Ronc
SEPIC rectifiers, when operating in DCM, do not require a
control loop for the input current because in this operation mode
[.005472
,. ] [.1306444
,. ] the converter emulates a load with resistive characteristic.
Therefore, the proposed rectifiers need only an output voltage
4 Ronc control, which is demonstrated in Fig. 9.
The equivalent electric circuit shown in Fig. 10 is used to
0 analyze the dynamic model for the output voltage in relation to
0 0.2 0.4 0.6 0.8 1 1.2 1.4 f s
Total charge - Tc Partial charge - Pc No charge - Nc the duty cycle of the proposed topology. It considers the average
Ronc = Ron + Rce ()a quantities and it is valid for small signals.
ic s ic s ic s The value of the current io illustrated in Fig. 10 is defined by
d I2 eq
io = . (8)
4M
t t t
()b ()c ()d
This current is modified when the output voltage (vo) or the
duty cycle (d) is changed. However, vo is also dependent on d.
Fig. 8. Switched-capacitor cell: (a) behavior of Req as a function of fs, (b)
Therefore, there is a correlation between the variables io, d and
current in CS for total charge mode, (c) current in CS for partial charge mode
and (d) current in CS for no charge mode.
vo, which has to be considered in the dynamic model.
Therefore, the output current is defined as
TABLE II
RANGES FOR THE OPERATING MODES OF CS
Operating mode Operating Interval Req regarding
minimal resistance
( ) dvo vo ,
(9)
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Cox1 =;Cox2 = (Co1 +CS1)+Co4 Co2 +Co3 , (11) (Co4 +CS1)Co1 C Co1 o4
Cox3 =;Cox4 =
(Co4 +CS1)+Co1 Co1 +Co4
( ) dvo vo .
(12)
io d v, o = Coeq +
dt Ro
DIeq D2 ,
( )=
v (13)
i d v, d
o o 2 o
2M 4M Leq sf
H vo
Fig. 9. Bloc diagram for the output voltage control.
iC oeq iRo
io (dv, o ) Coeq Ro vo
Fig. 10. Equivalent circuit of the output for voltage control. Fig. 11. Dynamic Model of the rectifier 2S with n = 2: (a) steady-state and
transient-state behavior, and (b) steady-state detail of vo and vmod.
TABLE IV
DESIGN SPECIFICATIONS
Specification Value
Input voltage 220 V
Frequency of the input voltage 60 Hz
Output voltage 800 V
Output power 1000 W
Switching frequency 50 kHz
Maximum duty cycle 0.35
Hold-up time 8.333 ms
Capacitors Ci1 and Ci2 ripple 20%
Inductor Li ripple 10%
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On applying the Laplace transform in (14) is obtained the transfer of 0.4 kW/kg and power density of 0.31 kW/L. It was built based
function on the specifications and list of components reported in Tables
IV and V, respectively. The experimental results were obtained
with the rectifier operating with rated power (1000 W) and in
TABLE V closed-loop.
LIST OF COMPONENTS The experimental waveforms for the voltage and the input
Component Specifications current are shown in Fig. 13. The current has a sinusoidal shape
Inductance: 3.385 mH and it is in phase with the respective voltage, even without a
Turns: 156 current control. It has a THD of 1.96% and power factor of
Inductor Li
Wire: 16 AWG 0.9991. Its harmonic spectrum is shown in Fig. 14,
Core: APH46P60
Inductance: 60.3 H
Turns: 29
Inductor Lo
Wire: 64 x 32 AWG Core:
EE42/20 3c94
Transistors S1 and S2 IPZ65R019C7 (650 V/19 m)
Diodes Do1 and Do2 MUR1560 (600 V/15 A)
Diodes De1 ... De6 C3D08060A (600 V/11 A)
Diodes D1 and D2 MUR860 (600 V/8 A)
Capacitors Ci1 and Ci2 B32672P5155K (1.5 F/520 V)
Capacitors Co1 Co4 B43845-A0158-M (2 x 1.5 mF/250 V)
Capacitors CS1 and CS2 C4AEGBW6100A3NJ (100 F/450
V)
Fig. 12. Photograph of the rectifier 2S with n = 2 implemented: A = Capacitors
CS1 and CS2; B = output capacitors; C = output inductors; D = input inductor;
vo ( ) s
E = capacitors Ci1 and Ci2; F = drivers for the switches S1 and S2.
k (15)
G s( )= =
d s( ) R Co oeqs+ Dk +1 vg
2Vo
iLi
which represents the converter model for small-signal average
values, where
k= DR Io eq . (16)
2M
T :5 ms
B. Validation of Dynamic Model for Control Fig.13. Input voltage (100 V/div) and input current (5 A/div) of the rectifier
The small-signal model proposed for the control was validated 2S with n = 2.
by numeric simulation using the specifications shown in Tables
IV and V. During the test, at t = 4.2 s the duty cycle is increased 2.5
in 1.4% and after 1.8 s (t = 6 s) the value returns to the standard
value. This procedure provided the output voltage waveforms of 2.0
the converter (Fig. 2) and of the model (15), which are shown in
Fig. 11 (a) and (b). The results reported in this figure demonstrate 1.5
that the proposed model adequately represents the converter in
IEC 61000-3-2 Limits
steady and transient states. It can be seen, as expected, that the 1.0
Harmonic Val ue
model does not represent the 120 Hz ripple and high frequency
ripple. 0.5
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times higher than the voltage of a classic SEPIC rectifier and
twice the voltage of the voltagedoubler SEPIC rectifier addressed
vo in [6], [9] and [10].
The experimental waveforms of the currents in the capacitors
iRo CS1 and CS2 are shown in Fig. 18. As in the case of the voltage,
the capacitor currents present two components: one at 60 Hz and
another at 50 kHz. The peak and rms values are close to 15 A and
5.9 A, respectively.
The voltage waveforms across the semiconductors S1-S2 and
Do1-Do3 are seen in Fig. 19 and Fig. 20, respectively. The voltage
stresses on these elements were 566 V-557 V and 565 V-562 V,
:5
Tms respectively. From the design specifications (listed in Table IV),
Fig. 15. Output voltage (100 V/div) and current (300 mA/div) waveforms of the theoretical maximum voltage applied on S1, S2, Do1 and Do3
the rectifier 2S with n = 2. is equal to 511 V, namely, the sum of
Fig. 16. Output voltage (100 V/div) and voltages on capacitors Co1, Co4 and
CS1 (50 V/div) of the rectifier 2S with n = 2.
Fig. 17. Output voltage (100 V/div) and voltages on capacitors Co2, Co3 and
CS2 (50 V/div) of the rectifier 2S with n = 2.
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with n = 2. Fig. 23. Voltages across the diodes De1, De2 and De3 (100 V/div) of the rectifier
2S with n = 2.
the peak value of the input voltage and a quarter of the output
voltage (for a case with two switched-capacitor cells). On the
vDo1 other hand, the conventional SEPIC rectifier with the same
specifications would have a theoretical voltage stress on the
semiconductors of 1111 V. Hence, it would be necessary to use
higher voltage devices, which would lead to higher conduction
losses.
The waveforms of the currents that flow through the
vDo3 components S1-S2 and Do1-Do3 are shown in Fig. 21 and Fig. 22.
These currents have one frequency component at 60 Hz and
T:10
s
another at 50 kHz. The rms values of the currents in switches S1
Fig. 20. Voltages across the diodes Do1 and Do3 (200 V/div) of the rectifier 2S and S2 are approximately 10 A and 9.5 A, respectively, while the
with n = 2. average values of the currents in Do1Do3 are 1.28 A and 1.2 A,
respectively.
The waveforms of the voltages across the diodes De1, De2 and
De3 are shown in Fig. 23. The voltage on De1 has a sinusoidal
envelope with frequencies of 60 Hz and 50 kHz. The maximum
iS1 voltage stress was 309 V. The measured voltages across De2 and
De3 also have one component in low frequency and another in
high frequency (60 Hz and 50 kHz, respectively). The
corresponding maximum values of these voltages are close to 204
V and 214 V.
The dynamic response of the converter to a load step of 41%
is demonstrated in Fig. 24. The output voltage presented an
iS 2
overshoot of 2% and settling time of 500 ms.
T:10
s
Fig.21. Current through the switches S1 and S2 (20 A/div) of the rectifier 2S
with n = 2.
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Fig. 27. Measured THD of the rectifier 2S with n = 2.
06.5%
VI. CONCLUSIONS
This paper proposed the integration of the single-phase
05.5%
voltage-doubler SEPIC rectifier with the switched capacitor (SC)
concept. As a result, a set of hybrid rectifiers was generated.
04.5%
These rectifiers improve the static gain of the voltage-doubler
SEPIC converter without increasing the voltage stress on the
03.5%
semiconductors, making them suitable for applications that
require high output voltage levels (above 800 V). The structures,
02.5%
a theoretical analysis and the experimental validation of this
integration are the main contributions of the paper.
01.5%
100 200 300 400 500 700 800 900 1000 The switched-capacitor cell integrated to the voltagedoubler
Output Power (W) SEPIC rectifier has extra diodes, which contribute to
TABLE VI
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QUANTITATIVE ANALYSIS
Bridgeless Bridgeless Bridgeless
Proposed Voltage Stress V V V
SEPIC SEPIC SEPIC
Characteristics Rectifier Rectifier Rectifier Rectifier on Switch Vg + o Vg +Vo Vg + o Vg + o
in DCM1 in DCM in DCM in DCM 4 2 2
[21]1 [10]1 [20]1 Voltage Stress V V V
on Switch for Vg + o Vg +Vo Vg + o Vg + o
Input current 0 0 0 0
control a n generic 2+ n 2 2
Voltage Stress V V V
Current sensor 0 0 0 0
on Diodes Vg + o Vg +Vo Vg + o Vg + o
Output voltage 1 1 1 1
4 2 2
control
Voltage Stress V V V
Voltage sensor 1 1 1 1 on Diodes for Vg + o Vg +Vo Vg + o Vg + o
Number of 2 2 2 2 a n generic 2 2
2+ n
Switches1
Rms current in
Number of fast 10 3* 2 7* 1 pu 0.844 pu 0.66 pu 1.34 pu
switches
diodes Avg Current in
Number of slow 2 2 2 2 1 pu 1 pu 1 pu 1 pu
Low Diode
diodes Avg Current in
Number of 3 2 3 2 1 pu 1 pu 1 pu 1 pu
Output Diode
inductors Rms Current
1 pu 0.72 pu 0.72 pu 1 pu
Number of 8 2 4 4 in Co1 and Co2
capacitors Rms Current
1 pu - - -
1 Bridgelessstructure implemented with two active in Co3 and Co4
switches. *The converter uses the intrinsic diodes of the Rms Current 1 pu - - 1.02 pu
switches. in CS1 and CS2
Rms Current
TABLE VII in SEPIC 1 pu 1.41 pu 1 pu 1.41 pu
QUALITATIVE ANALYSIS Capacitor
Bridgeless Bridgeless Bridgeless PF 1 1 1 1
Proposed SEPIC SEPIC SEPIC The proposed converter employs a three-state switching cell,
Characteristics Rectifier in Rectifier Rectifier Rectifier which can be implemented in three forms. Of these, the
DCM1 in DCM in DCM in DCM bridgeless version with two active switches (Fig. 1 (c) - 2S) was
[21]1 [10]1 [20]1
chosen for the theoretical analysis and experimental verification.
Static gain 2 2 2 2 The converter implemented was tested at rated power (1 kW) and
DR o DR o DR o DR o
4 Leqsf 4 Leqsf 4 Leqsf 4 Leqsf it provided a current with a THD of 1.96%, PF of 0.999 and
efficiency of 93.9%. These results are significant because the
rectifier does not use the soft commutation technique and
operates in DCM.
ACKNOWLEDGMENT
The authors would like to thank the Brazilian governmental
agency CNPq (National Council for Scientific and
Technological Development) for its contribution to this work in
the form of a grant provided to Paulo Junior Silva Costa.
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1
Bridgeless structure implemented with two active of additional switched-capacitor cells and in this paper it is
switches. generalized for n cells. Additionally, the rectifiers operate with a
fixed duty cycle, which reduces the losses from the switched-
obtaining a high quality input current. The static gain of the capacitor cell.
proposed converters can be easily increased through the insertion
c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more
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Technology Paran (UTFPR), Ponta
283288.
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Grossa, Brazil. He received the Ph.D.
conduction mode Sepic and Cuk power factor preregulators: analysis degrees in electrical engineering from the Federal University of
and design, IEEE Trans. Ind. Electron., vol. 44, no. 5, pp. 630637, Santa Catarina (UFSC) in 2017. His interests include PWM
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Nov. 2011. Carlos Henrique Illa Font (S04M09)
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of a Modular Three-Phase SEPIC-DCM Rectifier for Small Wind Sul, Brazil. He received the B.S., M.S. and
Energy Conversion Systems, in Proc. ISIE, 2015, pp. 439445. Ph.D. degrees in electrical engineering from
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232238.
2003 and 2009, respectively.
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SwitchedCapacitor PWM PFC Rectifier for High-Voltage-Gain He is currently an Adjunct Professor
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3505, May 2016. Engineering, Federal University of Technology Paran,
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power converters for small-scale renewable energy.
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Dr. Illa Font is a Member of the Brazilian Power Electronic
AC-AC converter, IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 735
745, Feb. 2015. Society, IEEE Power Electronics Society and IEEE Industrial
[19] P. J. S. Costa, C. H. Illa Font, T. B. Lazzarin, Single-Phase SEPIC Electronics Society.
rectifier with double voltage gain provided by a switched capacitor cell,
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c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more
Telles Brunelli Lazzarin (S09M12) was
born in Cricima, Santa Catarina
State, Brazil, in 1979. He received the
B.Sc., M.Sc. and Ph.D. degrees in Electrical
Engineering from the Federal
University of Santa Catarina (UFSC),
Florianpolis, Brazil, in 2004, 2006 and
2010, respectively.
He is currently an Adjunct Professor at the Department of
Electrical and Electronic Engineering (EEL) from the UFSC,
and he also works as a Researcher at the Power Electronics
Institute (INEP), UFSC. His interests include
switched-capacitor converters, inverters,
rectifiers, parallel operation of converters, highvoltage dc-dc
converters and conversion systems for small wind turbines.
Dr Lazzarin is a member of the Brazilian Power Electronic
Society (SOBRAEP), IEEE Power Electronics Society (PELS)
and IEEE Industrial Electronics Society (IES).
c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more