892 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO.
4, APRIL 2017
Low Latency and Low Error Floating-Point
Sine/Cosine Function Based
TCORDIC Algorithm
Baozhou Zhu, Yuanwu Lei, Yuanxi Peng, and Tingting He
Abstract CORDIC algorithm is suitable to implement
sine/cosine function, but the large number of iterations lead
to great delay and overhead. Moreover, due to finite bit-width
of operands and number of iterations, the relative error of
floating-point sine or cosine is terrible when the input angle
is close to 0 or /2, respectively. To overcome these short-
comings, TCORDIC algorithm, which combines low latency
CORDIC and Taylor algorithm, is presented. After analyzing
the latency of traditional CORDIC, low latency CORDIC is
proposed, which adopts the technique of sign prediction, com-
pressive iterations, and parallel iterations. Besides, the calcu-
lating boundary (N), which is used for determining whether
Taylor algorithm is selected or not in TCORDIC algorithm,
is evaluated to achieve a trade-off between area and delay.
Truncated multipliers are used to reduce the area further.
Finally, Using TCORDIC algorithm, pipelined and iterative
structures are implemented for IEEE-754 double precision
floating-point sine/cosine with the input Z[0, /2]. Under
typical condition (1V, 25 C), our designs are synthesized
with 40 nm standard cell library. For a pipelined structure,
the frequency is up to 1.70 GHz and area 194049.64 m2 .
Frequency decreases to 1.45 GHz for iterative structure, but
the area requires only 110590.81 m2 . TCORDIC is efficient in
controlling relative error, and achieves the accuracy within one
ulp (unit in the last place) for floating-point sine/cosine function.
Index Terms CORDIC, floating-point sine/cosine, low latency,
Taylor.
I. I NTRODUCTION
I N the fields of system control, simulation [1], high per-
formance computation [2], and scientific computation [3],
floating-point sine/cosine function with low error is essential.
In Intel 8087, Motorola, Cyrix coprocessors and CPUs such as
486DX and Pentium [4], sine/cosine is computed in hardware.
FPGA and ASIC provide suitable platforms for implementa-
tion of sine/cosine.
Algorithms for sine/cosine function on hardware are divided
into three categories: look-up table, polynomial approximation
and digital iteration [4]. Look-up table is applicable to low
precision [5], because hardware cost grows exponentially with
precision. The convergence speed of polynomial approxima-
tion is fast for a small variable, but decreases rapidly as the
Manuscript received August 8, 2016; revised October 22, 2016; accepted
November 13, 2016. Date of publication December 15, 2016; date of current
version March 27, 2017. This work is supported by National Natural Science
Foundation of China, NO: 61402499. This paper was recommended by
Associate Editor Y. Pu
The authors are with the School of Computer, National University of
Defense Technology, Changsha 410073, China (e-mail: 2278125123@qq.com;
yuanwulei@nudt.edu.cn; pyx@nudt.edu.cn; heting7410@qq.com).
Digital Object Identifier 10.1109/TCSI.2016.2631588
1549-8328 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
variable increases. Thus, the required number of multiplica-
tions and additions turns out to be larger. Typically, polynomial
is combined with look-up table [3]. The variable is compressed
to a smaller range by look-up table, and polynomials calculate
final results quickly. However, this combination is still expen-
sive to implement the multipliers, adders and tables for high
precision sine/cosine computation.
CORDIC algorithm is a kind of digital iteration method
to calculate a variety of transcendental functions, including
sine/cosine function in circular coordinate and rotation
mode. Calculating sine/cosine function based on CORDIC
algorithm has been employed [6] for a variety of high-speed
and real-time applications, such as adaptive filters [7] in
digital signal processing (DSP), discrete sinusoidal transforms
[8] in signal processing, generating sinusoidal waveforms
[9] in communication, robot control [10], and geometric
computations [11] in graphics.
However, a large number of iterations must be executed
in order, which is the a bottleneck for optimization of
CORDIC. The first data dependence is determination of the
rotation direction by iteration results of Z path. The second,
which refers to the (i + 1)t h iteration, can be started only
after the completion of the i t h iteration, because the micro-
rotations for any iteration are performed on the intermediate
vectors computed by the previous iterations. These two data
dependence restricts optimization of the critical path. In
addition, each iteration is completed by carry look ahead
adder, and the delay due to carry propagation is proportional
to the bit-width of operands. Therefore, when the precision
requirements are higher, the bit-width of operands and carry
propagation delay increase.
The precision of CORDIC converges linearly with the
number of iterations. Error is inevitable because of the finite
bit-width of operands and the number of iterations. And,
relative error is too large to meet the precision requirements
for IEEE754 floating-point standard.
TCORDIC algorithm, combining low latency CORDIC with
Taylor algorithm, is presented to efficiently control relative
error for floating-point sine/cosine function. Moreover, low
latency CORDIC is proposed by combining sign predic-
tion, compressive iterations, and parallel iteration techniques.
Pipelined and iterative structures are implemented, and N for
the calculating boundary, which is used for determining
whether Taylor algorithm is selected or not in TCORDIC
algorithm, is evaluated to achieve the balance between area
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM
and delay. In addition, truncated multipliers further reduce
the area. The following are the main advantages of our
designs:
1) The accuracy of floating-point sine/cosine function is
guaranteed within one ulp (unit in the last place).
By combining Taylor and CORDIC, absolute and rel-
ative error can be controlled effectively with the input
Z [0, /2], to achieve of the precision requirements of
IEEE754 floating-point standard.
2) The proposed low latency CORDIC combines the
schemes of sign prediction, compressive iterations, and
parallel iterations, which significantly reduces area and
delay.
3) By selecting Taylor appropriately, pipelined structure
obtains low latency with maximum possible reduction
in area, and iterative structure makes full use of low
area cost with maximum possible reduction in delay.
4) By optimizing the bit-width of truncated multiplier for
meeting the precision requirements, the area can be
further reduced.
II. BACKGROUND AND R ELATED W ORK
A. Traditional CORDIC Algorithm
Sine/cosine function is calculated in rotation mode and cir-
cular coordinate. The following are the basic iterative formulas
for such calculation:
i
X i+1 = ki (X i i 2 Yi )
i
Yi+1 = ki (Yi + i 2 X i ) (1)
Z i+1 = Z i i i .
Where, i {1, 1} refers to sign(Z i ), which determines the
rotation directions of the vector, and i = tan 1 (2i ) is the
micro-rotation angle. ki = 1 2i , and the scale factor after
 (1+2 )
n iterations is K n = ni=1 ki . Initial angle Z 0 is the rotation
angle in total, and the iterations make Z i approach 0. The
vector corresponding to Z 0 can be obtained after n iterations.
 around 0 , which aims to improve only frequency resolution
X n = K1n (X 0 cos(Z 0 ) Y0 si n(Z 0 ))
(2)
Yn = K1n (Y0 cos(Z 0 ) + X 0 si n(Z 0 )).
With X 0 = K n ,Y0 = 0, the iteration results are equivalent to
sine and cosine for Z 0 in the range of Z 0 [0, /2].
B. Related Work
Since Volder proposed CORDIC algorithm to calcu-
late trigonometric function in 1959 [12], [13], many vari-
ants [14], [15] are presented to reduce delay. Reducing the
number of iterations [16], [17] and reducing the delay of
each iteration are the two main prerequisites for achieving low
latency. Carry-free adder is a straight-forward choice to reduce
the delay of each iteration. Parallel CORDIC [18], [19] speeds
up iteration period by CSA (Carry Save Adder), and multi-
operand CSA tree architectures are adopted to replace the last
half of the iterations. However, both the delay and the area
for CSA trees are large, and sign prediction for all iterations
requires much area. Redundant CORDIC [16], [20], [21] uses
a redundant representation and the corresponding adder to
893
achieve a fast carry-free computation. There are two types of
redundant numbers: carry-save and signed-digit [20]. Redun-
dant CORDIC can significantly reduce iteration period, but
both the scale factor and the number of iterations are variable.
Besides, sign prediction for redundant numbers increases
implementation complexity. High-radix CORDIC [16], [21],
[22], [23] needs fewer iterations than radix-2 CORDIC does.
But, with a variable scale factor, both the look-up table for
scale factor calculation and compensation lead to a great
delay and area. The drawback inherent to the scaling-free
CORDIC [24], [25] lies in its small convergence range,
whether the domain folding technique or the repetitions of
the first elementary micro-rotation lead to great cost and
delay.
Sang [26] points out that tangle approximation and round-
off are the two main sources of error in CORDIC algorithm.
By choosing appropriate bit-width of operands and number
of iterations, absolute error of fixed-point CORDIC can be
controlled and measured by MSE (mean-square-error), but
relative error remains ignored. Therefore, Hu [27] finds that
when the input vector is close to 0 in vector mode, relative
error caused by round-off is maximum and sufficient enough
to misinterpret rotation directions. The partial normalization
scheme proposed by Kota [28] and the prescaling technique
adopted by E. Antelo [29] can decrease the relative error.
However, researchers [30] analyzed only absolute and relative
errors of fixed-point CORDIC, but made no mention of error
analysis and control for floating-point CORDIC.
Anis [31] compares CORDIC with Taylor algorithm to
calculate sine/cosine function about structure and precision
in detail, but his focus is on the contrast rather than the
combination. Daniel [32] combines CORDIC with Taylor
algorithm for calculation of floating-point exponential function
to improve precision, without elaborating the principle and
generalizing it to sine/cosine function. Maher [33] uses one
CORDIC to replace two Read Only Memories to compute sine
and cosine of the upper address 0 , with Taylor computing
for Direct Digital Frequency Synthesizer.
III. TCORDIC A LGORITHM
TCORDIC algorithm, combining low latency CORDIC and
Taylor algorithm, is proposed in this section to improve
the accuracy of floating-point sine/cosine computation of
CORDIC when the input angle is close to 0 or /2, and
guarantee the accuracy within one ulp.
A. Low Latency CORDIC Algorithm
1) Delay Analysis for Traditional CORDIC: The delay for
traditional CORDIC is determined by the number of iterations
and the delay of each iteration. In pipelined structure, X/Y
path is critical and Delay = n (TnC L A + Treg ), where
TnC L A and Treg refer to the delay for n-bit Carry Look
ahead Adder and register, respectively. In iterative structure,
the worst path is determined by the maximum delay in X, Y
and Z paths. As shown in Fig. 1, Delay = max{n(TnC L A +
Tbshi f t (n,log2 n) + Treg ), n (TnC L A + TLU T + Treg )}, where
894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017

Plugging the i t h iteration formulas into the (i + 1)t h , the

following formulas are available:

X i+2 = X i (1 i i+1 22i1 ) Yi (i 2i + i+1 2i1 )
Yi+2 = Yi (1 i i+1 22i1 ) + X i (i 2i + i+1 2i1 ).
(6)
In this way, the iteration formulas between the m t h and the
Fig. 1. Iterative structure based on traditional CORDIC. (n 1)t h are expanded:
.

X n = X m Am,n Ym Bm,n


TLU T and Tbshi f t (u,v) refer to the delay for look-up table

and u-bit barrel shifter of v control signals, respectively. Yn = Ym Am,n + X m Bm,n


 


The delay can be decreased significantly by reducing the
Am,n = 1 i j i j 2i j


number of iterations, and the main delay of each iteration
   

+ i j k l i j k l 2i j kl
deriving from CLA. Due to linear convergence of CORDIC,

the bit-width of operands and the number of iterations increase   i(1)..i(2t )

.. + (1) t
i(1) .. i(2t ) i(1) .. i(2t ) 2 (7)
linearly with precision. High precision requirement causes



great delay in carry propagation. Bm,n =  i 2i    i j k 2i j k


2) Sign Prediction Scheme: Low latency CORDIC algo-
i i j k

 
rithm eliminates the first data dependence by using sign


+.. + (1)t i(1) .. i(2t +1) i(1) ..i(2t +1)
prediction technique in Z path. The binary expression of Z j is

n

j
j =0 b j 2 , b j {0, 1}. If Z j = b0 , b1 , . . . , b j 1 b j , . . . , bn

2 i(1)..i(2t +1)

and b0 = b1 = = b j 1, transformation rule of sign

prediction between the j t h and k t h bits is defined as follows:
if Z j is positive or in other word b j 1 = 0, j is equal to 1;
otherwise, j is equal to -1. Since i > j 1, i+1 is equal to
-1 if bi = 0, and i+1 is equal to 1 if bi = 1.
Angle approximation error of each iteration in this rule is
2i i , and the cumulative error of k i + 1 iterations must
be less than 2n to ensure convergence. So, k 3i + 1 must
be satisfied. With index i (n log2 3)/3, it can be known
that 2i i < 2n . Thus, i can be replaced with 2i ; so, the
last 2/3 iterations adopt transformation rule of sign prediction
directly. With index i < (n log23)/3, correct iterations are
added to ensure prediction accuracy in the iteration sequence
according to k 3i + 1.
3) Compressive Iterations Based on CSA: Based on sign
prediction, the first half of the iterations are compressed by
CSA in X and Y paths. CSA eliminates carry propagation
delay of each compressive iteration and makes it irrelevant to
the bit-width of operands. X i and Yi are divided into sum and
carry, respectively.
 (9)
X i = X i C + X i S
Yi = Yi C + Yi S .
The iteration formulas are converted as (4), where CLAs
in X and Y paths are replaced with 4:2 CSAs.
 B. Error Analysis for Floating-Point Sine/Cosine
C + X S = X C + X S 2i (Y C + Y S )
X i+1 i+1 i i i i i
(4)
C S C S i
Yi+1 + Yi+1 = Yi + Yi + i 2 (X i + X i S ).
C of floating-point sine/cosine function is large, due to the
4) Parallel Iterations Based on Multiplication: The last half
of the iterations are calculated by parallel iterations, which
eliminate the second kind of data dependence and reduce the
number of iterations. The formulas of the i t h iteration are as
follows: 
X i+1 = X i i 2i Yi
(5)
Yi+1 = Yi + i 2i X i .
where i, j, k, i (1), . . . , i (2t), i (2t + 1) are all integers from m
to n 1, and satisfied m 1 < i < j < k < n, m 1 < i (1) <
i (2)... < i (2t) < i (2t + 1) < n. When m n/2 + 1, it can be
known that i + j 2m + 1 n + 3. Except the first item 1
in Am,n , the maximum sum of other items is less than 2n1 .
Except the first item i i 2(i) in Bm,n , the maximum sum
of other items is less than 2n2 . Because of Ym 1 and
X m 1, the error of X n or Yn is less than 2n , as analyzed
in the Appendix.
Thus, iterations from the (n/2 + 1)t h to the (n 1)t h can
be simplified as follows:
 
X n = X n/2+1 Yn/2+1 ni=n/2+1 i 2i
 (8)
Yn = Yn/2+1 X n/2+1 ni=n/2+1 i 2i .
The last half ofthe iterations can be regarded as the
rotation with angle ni=n/2+1 i 2i , which is equal to Z n/2+1 .
Therefore, the formulas are converted as follows:

X n = X n/2+1 Yn/2+1 Z n/2+1
Yn = Yn/2+1 X n/2+1 Z n/2+1 .
(3) Thus, the last half of the iterations can be completed with
two multipliers and two adders.
When the input is close to 0 or /2, the relative error
following errors:
1) Angle Approximation Error: Angle approximation error
comes from finite number of iterations. The resolution of
results is 2n after n iterations; so, the angle approximation
error approaches 2n . Absolute error is smaller as the number
of iterations is larger. However, the magnitude of error is rel-
ative to the exponent under IEEE-754 floating-point standard.
To round off correctly, absolute error should be less than
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM 895

2 E Z Eo f f set L , assuming that Z = (1) S Z M Z 2 E Z . L

represents bit-width of mantissa in normalized form, and there
are 23 and 52 bits respectively for single and double precision
floating-point in IEEE-754 standard. It can be proved that
Z /2 < si n(Z ) < Z (E Z E o f f set < 0) with 0 < Z < /3;
so, the number of iterations needs more than L + 1
(E Z E o f f set ) to guarantee precision. Therefore, required
number of iterations increases as the input decreases.
2) Round-Off Error: Round-off error is inevitable and is
caused by finite bit-width of operands. The operands adopt Fig. 2. Error analysis with N  < 10.
fixed-point format, including 1 bit for sign, N1 bits for integer
and N2 bits for decimal. N2 increases as the precision required
increases. To ensure relative error less than 2 E Z Eo f f set L ,
decimal is at least L + 1 (E Z E o f f set ) bits. In addi-
tion, taking into account the round-off error accumulated
by L + 1 (E Z E o f f set ) iterations, there are at least
log2 (L + 1 (E Z E o f f set )) guard bits. Therefore, the bit-
width of operands requires 1 + N1 + L (E Z E o f f set ) +
log2 (L + 1 (E Z E o f f set )) bits to ensure precision, and
this increases with decreasing input.
The bit-width of operands, which does not include the bits Fig. 3. Error analysis with N  > 10.
for sign and integer, refers to n and is equal to the number of
iterations. To guarantee the accuracy of L mantissa bits under
IEEE754 floating-point standard, the following equation must the key issue in to guarantee precision is solving the problem
be satisfied: with a small input. Luckily, Taylor has a fast convergence
speed with a small variable. With floating-point input Z ,
L + 1 (E Z E o f f set ) + log2 n n. (10) Taylor expansion is expressed as follows:
To guarantee precision, the required number of iterations c Z 2i1
and bit-width of operands will have to be increased whenever si n(Z ) = Z Z 3 /3! + (1)i+1
i=3 (2i 1)!
the input is smaller, and this leads to sharp increase in
c 2i1 (2i1)(E Z E o f f set )
hardware cost. According to si n(Z ) = cos(/2 Z ), when i+1 M Z 2
= (1) . (11)
Z is close to /2, the relative error of cos(Z ) is similar to i=1 (2i 1)!
that of si n(Z ), Z being close to 0. If the number of expansion items is c, the omitted
3) A Specific Example of Relative Error of Sine: The (2c+1)(E Z E o f f set )
M 2c+1 2
relative error of sine can be clarified with a specific example. sum of Taylor expansion is less than Z (2c+1)! .
With input Z [0, /2], the bit-width of operands and number To guarantee the accuracy of L mantissa bits, relative error
of iterations is 64, and the guard bits are log2 64 = 6 bits. N  is must be less than 2 E Z Eo f f set L ; the following equation must
equal to E o f f set E Z and refers to the number of leading zeros be satisfied.
of Z 0 . Z 0 is the fixed-point form of Z and includes 1 sign bit, M Z2c+1 2(2c+1)(E Z Eo f f set )
1 integer bit and 62 decimal bits. < 2 E Z Eo f f set L . (12)
(2c + 1)!
With N  < 10, as shown in Fig. 2, and the sine of Z in
fixed-point form is only two cases of si n(Z 0 ) or si n(Z 0 ) ,
   C. TCORDIC Algorithm
because 2N 1 < si n(2N ) < 2N . After normalizing, all
bits of mantissa of si n(Z ) in floating-point form come from TCORDIC algorithm, as shown in Fig. 4, is composed of
the iterations of Z 0 , but they may include guard bits, which low latency CORDIC and Taylor algorithm, whose respec-
may be inaccurate. At the end, there are six guard bits, which tive advantages are mutually complementary in computing
may or may not be abandoned due to normalization. floating-point sine/cosine function, achieving the accuracy
Similarly, with N  > 10, the sine of Z is also two cases of within one ulp. As the convergence speed of Taylor is fast with
si n(Z 0 ) or si n(Z 0 ) , as shown in Fig. 3. After normalizing, a small variable, Taylor is used as a supplement to CORDIC.
mantissa bits of si n(Z ) in floating-point form come from the In TCORDIC, N refers to the calculating boundary that can
iterations of partial bits of Z and complementary 0 bits. The determine whether Taylor algorithm is selected or not. For
bits of mantissa iterated from 0 bits must be inaccurate, and sine, it is computed by Taylor when E o f f set E Z > N,
those iterated from the bits of Z include 6 guard bits. With otherwise it is computed by CORDIC. For cosine, it is
the increase of N  , the guard bits and inaccurate bits iterated calculated by Taylor when E o f f set E Z > N, where E Z refers
from 0 bits approach high bits of mantissa, and the relative to the exponent of /2 Z 0 after normalizing, otherwise it is
error becomes larger. calculated by CORDIC.
4) Error Analysis for Taylor Algorithm: In the case of finite When E o f f set E Z N, to guarantee accurate L
bit-width of operands and number of iterations in CORDIC, bits of mantissa, n min can be known according to (10)
896 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017

Fig. 5. Delay influence of N in TCORDIC, where N is the calculating

boundary, h is the number of cycles to calculate Taylor expansion, and a is
the number of cycles to complete compressive iterations in CORDIC.

A. Iterative Structure
1) Optimization of the Calculating Boundary (N): Iterative
structure needs only a truncated and fixed-point multiplier.
During iteration for CORDIC, the multiplier is multiplexed
for Taylor. Calculation for Taylor expansion adopts Horner
scheme, which involves the least multiplications.
Z 3 c Z 2i1
si n(Z ) = Z + (1)i+1
3! i=3 (2i 1)!

Fig. 4. TCORDIC algorithm.
where E o f f set E Z = N,
L + 1 + N + log2 n min n min . (13)
Similarly, when E o f f set E Z > N, to guarantee accurate
L bits of mantissa, cmin can be known according to (12) where
E o f f set E Z = N.
M Z2cmin +1 2(2cmin +1)(N)
< 2NL . (14)
(2cmin + 1)!
IV. I MPLEMENTATIONS OF TCORDIC
In this section, IEEE-754 double precision floating-point
is taken as an example to illustrate the implementations of
TCORDIC algorithm.
To guarantee accurate mantissa, where L = 52 bits for
double precision floating-point computation, the number of
iterations, as also the bit-width of operands n min in CORDIC,
and the number of expansion items cmin in Taylor required to
calculate minimally relate with the calculating boundary (N),
which refers to (13) and (14). Therefore, the calculating
boundary (N) can be optimized to achieve a trade-off between
area and delay. The optimal values of the calculating bound-
ary (N) are 13 and 5 in pipelined structure and iterative
structure, respectively.
2 1 2 1 Z2
= Z 1 Z ..Z .. .
3! (2c 3)! (2c 1)!
(15)
In CORDIC, a 2-stage compressive iteration occupies one
clock cycle. In a multiplication, the first 2-stage compression
accounts for one clock cycle, and the last 2-stage compres-
sion and addition with CLA account for one clock cycle.
In Taylor, shift and addition account for one clock cycle
in total. The required number of cycles with the truncated
multiplier multiplexing is h for Taylor expansion, and a for
completing the compressive iterations in CORDIC. Therefore,
the time constraint is h a, and the truncated multiplier had
better be multiplexed as much as possible. While the number
of iterations in CORDIC is n min , the number of cycles to
compress is
a = n min /4 . (16)
With cmin Taylor expansion items, the truncated multiplier
is multiplexed cmin + 1 times, and there are cmin 1 additions
and shifts. Therefore, the total number of cycles for Taylor
expansion is
h = 3(cmin 1) + 4. (17)
With L = 52 bits to be guaranteed, (13), (14), (16), and (17)
are used in computing. As shown in Fig. 5, the time constraint
h a can be satisfied with N 5. when N continues
to increase, the number of iterations required to guarantee
precision increases. Therefore, N = 5 for the calculating
boundary is the optimal value in iterative structure.
2) Parameters and Process Illustrations: The implementa-
tion of the overall iterative structure is shown in Fig. 6(A).
According to the above analysis, the key parameters for the
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM
Fig. 6. Implement of iterative structure.
implementation of the optimized iterative structure are as
follows:
Guaranteed precision L = 52 bits.
Calculating boundary N = 5. For sine, it is computed
by Taylor when E o f f set E Z > 5 (i.e., Z [0, 25 ]),
otherwise it is computed by CORDIC. For cosine, it is
calculated by Taylor when E o f f set E Z > 5 (i.e., Z 
[/225 , /2]), otherwise it is calculated by CORDIC.
The number of iterations, as also the bit-width of
operands in CORDIC n min = 64.
The number of Taylor expansion items is cmin = 5.
In CORDIC path, the first 32 iterations are completed by
compressive iterations, and the last 32 iterations are completed
by parallel iterations, which multiplexes a 53*53-bit truncated
multiplier twice. In addition, the sign prediction scheme con-
sists of three levels, predicting directions for the 1t h 4t h ,
5t h 12t h , and 13t h 32t h iterations.
In Taylor path, the 53*53-bit truncated multiplier is multi-
plexed 6 times to calculate the first 5 expansion items.
3) Preprocessing: The preprocessing module determines
whether Taylor is selected according to the input Z , whose
original floating-point form is transformed into fixed-point
form Z 0 . As shown in Fig. 6(B), Z , which is an IEEE-754
897
double precision floating-point number, includes exponent E Z
and mantissa M Z . If E o f f set E Z is greater than 5, Taylor is
selected to calculate si n(Z ). If E o f f set E Z is greater than 5,
Taylor is selected to calculate si n(/2 Z 0 ), which is equal
to cos(Z ). To calculate (/2 Z 0 ), the adder needs 52 + 64
bits guaranteed even in the worst case that the 52 high bits
of (/2 Z 0 ) are all 0. To calculate by Taylor, (/2 Z 0 )
is normalized. Whether or not Taylor is selected, CORDIC
calculation always works to calculate sine and cosine.
4) Compression and Prediction: Compression and
prediction module complete rotation direction prediction and
compressive calculation in Z path. To guarantee accurate
prediction, correction iterations must be carried out; so, CSA
and CLA are mixed in Z path. CLAs are used in the position
of correction iterations for summations, and CSAs between
correction iterations for compression. A series of micro-
rotation angles for iterations are predefined; so, segmented
look-up tables are adopted. Therefore, a number of iterations
can be replaced with an addition and a table look-up. Besides,
sign prediction makes compressive calculation with CSA
available in Z path. In the first 32 iterations, correction
iterations have to be added at positions i = 1, 4, 12, and
hence the prediction module is composed of 3 submodules.
898 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017
Fig. 7. The structure of a 4-stage compressive iteration.
In these submodules, Z 4 , Z 33 and Z 12 are calculated and the
corresponding rotation directions predicted.
The structure of the second prediction submodule, including
a look-up table with rotation angles (32 64bits), is shown
in Fig. 6(C). The bits Z 4 [59 : 52] are the key elements in the
submodule. On the one hand, the bits determine the operations
of addition and subtraction in X and Y paths, and on the other,
they index the look-up table for ar ctan_4 and ar ctan_8.
In the third prediction submodule, the bits Z 12 [51 : 30]
account for predicting rotation directions from 13 to 32 ;
besides, they index a series of rotation angles to accumulate.
The compression structure with CSAs in the third submodule
is shown in Fig. 6(C). Finally, a CLA is used to calculate
the summation of Z 32 , which will be a multiplier for parallel
iterations in CORDIC.
5) Compressive Iteration Multiplexing: Compressive itera-
tion multiplexing module completes compressive iterations in
X and Y paths for CORDIC. According to sign prediction,
each multiplexing needs 2 clock cycles, and the first 32 com-
pressive iterations multiplex this module 8 times in segmented
cycles. Both the inputs and outputs of the multiplexing module
in X and Y paths are divided into carry and sum, and the
outputs become the inputs for the next multiplexing, as shown
in Fig. 6(D). The counter provides the multiplexing module
with the selection signal S1 , which records the number of times
the multiplexing module has been multiplexed and accordingly
determines the bits to shift.
The structure of the multiplexing module is a 4-stage
compressive iteration, as shown in Fig. 7. As CSA is better
than CLA in terms of area and delay, the CLAs are replaced
with CSAs to complete compressive iterations.
6) Truncated Multiplier Multiplexing: The truncated multi-
plier multiplexing module completes calculation of 5 expan-
sion items for Taylor and parallel iterations for CORDIC.
For ensuring 53 high bits of final and accurate results,
a 53 53-bit fixed-point and truncated multiplier is adopted
with an output of 59 bits, which includes 6 guard bits and
53 accurate bits. In CORDIC, 32 high bits of Z 33 become
the same as sign(Z 33) after 32 compressive iterations, and
only its 32 low bits participate in subsequent multiplication.
To guarantee 32 high bits of the truncated multiplier out-
put accurate, a 32 32-bit truncated multiplier is adopted,
outputting 38 bits, which consists of 6 guard bits and
32 accurate bits. Considering a truncated multiplier mul-
tiplexing for CORDIC and Taylor, a 53 53-bit truncated
multiplier, outputting 59 bits, is adopted (see Fig. 6(E)), which
is composed of 6 guard bits and 53 accurate bits.
After preprocessing, Taylor is not selected with
sel|sel = 0, and the truncated multiplier remains free
during the first 16 clock cycles. If sel|sel is 1, the truncated
multiplier is multiplexed 6 times to calculate the first
5 expansion items for Taylor. A multiplication requires
2 clock cycles, and an addition and a shift together need
a clock cycle. The first step is to calculate M Z2 in the
first 2 clock cycles, and the second step is to circulate
4 times. Each circulation needs 4 clock cycles in the order
of multiplication, shift and addition, the last step being the
multiplication of the intermediate result by M Z to obtain the
final result (see Fig. 6(E)).
7) Post-Processing: The post-processing module, shown
in Fig. 6(F), normalizes the final results and selects si n(Z )
and cos(Z ) from the outputs of Taylor and CORDIC paths.
The normalization module is used to transform the final results
from fixed-point form to floating-point form. In addition,
the final results are selected from the outputs of Taylor and
CORDIC paths according to the valid signals sel and sel  .
B. Pipelined Structure
1) Optimization of the Calculating Boundary (N):
In pipelined structure, the direct method of calculating Taylor
expansion is adopted. For calculating cmin items for Taylor
expansion, the required number of multipliers is
m = 2cmin 1(cmin > 1). (18)
With L = 52 bits to be guaranteed, (13), (14), and (18) are
used in computing. As shown in Fig. 9, m and n min change
with N, and the trends are diametrically opposite. Therefore,
there is an optimal value for N to achieve the least area. With
N = 1, 2, 3, 4, 6, 8, 13, the number of iterations is minimum
when the number of multipliers is the same; so, choosing
between these points is a matter of priority. When N < 13,
the number of iterations increases with increase of N, but the
number of multipliers decreases rapidly. On the other hand,
when N > 13, decreasing the number of multipliers results
in a great increase of the number of iterations. Therefore,
N = 13 for the calculating boundary is the most suitable
value in TCORDIC.
2) Parameters and Process Illustrations: The implementa-
tion of pipelined structure is shown in Fig. 8. According to
the above analysis, the key parameters for the implementation
of the optimized pipelined structure are as follows:
Guaranteed precision L = 52 bits.
Calculating boundary N = 13. For sine, it is computed
by Taylor when E o f f set E Z > 13 (i.e., Z [0, 213 ]),
otherwise it is computed by CORDIC. For cosine,
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM 899

Fig. 10. Bit-width simplification.

and two 53 53-bit multipliers are needed to obtain two inter-

mediate results of 106 bits. Finally, X 3 /6 is computed with a
106 106-bit multiplier. As shown in Fig. 10, two 53 53-bit
multipliers are replaced with two M M-bit truncated mul-
tipliers, and the intermediate results are of M1 bits, instead
Fig. 8. The overall pipelined structure. of 106 bits. There are (M1 M2 ) guard bits. Small circles
filled with gray color stand for the error generated from
the truncation, and formula (19) can ensure the accuracy
of M2 bits in the M M-bit truncated multipliers.

M 2(M1 2) < 2(M2 2) . (19)

Similarly, the 106 106-bit multiplier is replaced with a

M2 M2 -bit truncated multiplier, and its output is L 1 bits,
including (L 1 30) guard bits. Formula (20) must be satisfied
to guarantee 30 accurate bits.

M2 2(L 1 4) < 2(304) . (20)

Fifty-three bits are replaced with M bits, and round-off error

of M Z is less than 2(M1) . As shown in Fig. 10, unfilled
Fig. 9. Area influence of N in TCORDIC, where N is the calculating circles represent round-off error in the multiplication, and the
boundary, m is the number of multipliers to calculate Taylor expansion, and error is less than 2(M1) 2(M1) + 2 21 2(M1) .
n min is the number of iterations and bit-width of operands in CORDIC.
it is calculated by Taylor when E o f f set E Z > 13
(i.e., Z [/2 213 , /2]), otherwise it is calculated by
CORDIC.
If 2(M 1)  (M2 2), formula (21) is required to guarantee
precision.
2 21 2(M1) < 2(M2 2) . (21)
Similarly, 106 accurate bits are replaced with M2 accurate
bits, and the round-off error of the intermediate results is
The number of iterations, as also the bit-width of
operands in CORDIC n min = 73.
The number of Taylor expansion items is cmin = 2.
In CORDIC path, the first 36 iterations are completed by
compressive iterations. The last 36 iterations are completed
by parallel iterations, which requires two 39 39-bit truncated
multipliers. In addition, the sign prediction scheme consists
of three levels, predicting directions for the 1t h 4t h ,
5t h 12t h , and 13t h 36t h iterations.
In Taylor path, two 34 34-bit truncated multipliers and a
32 32-bit truncated multiplier are adopted to calculate the
first 2 expansion items.
3) Bit-Width of Truncated Multipliers: In pipelined struc-
ture, two expansion items for Taylor need to be calculated
with N = 13. Thirty bits of X 3 /6, which later participate
in summation, must be accurate. Mantissa M Z is 53 bits,
generated. If 2(M2 2)  26, formula (22) needs to be
satisfied to meet precision.
2 22 2(M2 2) < 226 . (22)
By solving (19), (20), (21), and (22), M2 32, L 1 36,
M 34, and M1 38 can be obtained.
In CORDIC path, the number of iterations, as also that
of bit-width of operands, is 73. Thirty-six high bits of
Z 37 have all become the same as sign(Z 37) after the first
36 iterations, and only 36 low bits participate in subsequent
multiplication. A M3 M3 -bit truncated multiplier is adopted,
outputting 36 accurate bits. As in the case of the foregoing
analysis, round-off error for multiplication needs to satisfy that
2M3 2 21 < 236 . Therefore, the 39 39-bit trun-
cated multiplier is adopted, outputting 42 bits, which
include 6 guard bits.
900 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017

TABLE I
S YNTHESIZED R ESULTS W ITH 40 nm S TANDARD C ELL L IBRARY

4) CORDIC Path: As shown in Fig. 8, the third prediction

submodule calculates Z 37 , instead of Z 33 , and the rest in
Z path is almost the same as that in iterative structure.
To reduce area and delay, the first 8 iterations [18]
in X and Y paths are completed by look-up table, instead of Fig. 11. Comparison of error bits of sine/cosine.
compression. The remaining compressive iterations are divided
into 14 ROTs, and each ROT, which is a 2-stage compressive TABLE II
iteration module. Two 39 39-bit fixed-point and truncated U NIFIED PARAMETERS OF C OMPONENTS
multipliers are adopted, outputting 42 bits, which include
6 guard bits and 36 accurate bits.
5) Taylor Path: Taylor path consists of 3 truncated multi-
pliers and a CLA. The outputs of the two 34 34-bit truncated
multipliers are intermediate results, and they are all 38 bits.
With 6 guard bits abandoned, the remaining 32 bits involve
in the multiplication of a 32 32-bit truncated multiplier. The
output of the 32 32-bit multiplier is 36 bits, and its 30 high
bits participate in last addition with M Z .

V. E XPERIMENTAL R ESULTS
A. Synthesis Results
Our designs are synthesized with 40 nm standard cell
library under typical condition (1V, 25 C). There is a
clock cycle constraint of 700 ps for iterative structure and
600 ps for pipelined structure, with 150 ps for input delay
and 150 ps for output delay. The synthesized results of
pipelined and iterative structures are shown in Table 1. For
pipelined structure, CORDIC path and Taylor path occupy area
176952.46 and 17097.18 m2 , respectively.
B. Accuracy Analysis
Because of finite bit-width of operands and number of
iterations in CORDIC, the relative error of floating-point sine
or cosine is terrible when the input is close to 0 or /2,
respectively. Jie [6] provided a relative error of 232 with a
small input for double precision floating-point sine computa-
tion, and the maximum relative error should be larger with a
smaller input.
The following comparison reflects the accuracy improve-
ment of our TCORDIC clearly. The number of inaccurate
bits of mantissa measure the relative error for floating-point
computation quantitatively, and the input is limited in the range
close to 0 or /2. Because of the symmetry of sine and cosine,
the number and trend of error bits for sine with Z close to 0
are similar to those for cosine with Z close to /2.
TCORDIC can guarantee faithful rounding (i.e., the error
is smaller than one ulp) for any angles in [0, /2]. Fig. 11
compares the relative error of sine or cosine between tradi-
tional CORDIC and TCORDIC when the input Z is close
to 0 or /2. The number of iterations, as also the bit-width
of operands, in traditional CORDIC is 64, the same as
those in TCORDIC. Five-hundred points are uniformly taken
during log2 Z [25, 5] to compute sine, and the
input Z correspondingly varies from 0x3e60000000000000
to 0x3 f a0000000000000. Similarly, five-hundred points
are uniformly taken with log2 (/2 Z ) [25, 5]
to calculate cosine, and Z correspondingly varies from
0x3 f f 911 f b54442d18 to 0x3 f f 921 f b53442d18.
As shown in Fig. 11, the error of traditional CORDIC is
large for fixed bit-width of operands and number of iterations,
and the error bits of sine or cosine increase quickly when the
input angle is close to 0 or /2, respectively. The error of sine
or cosine of TCORDIC is no more than one error bit with the
supplement of Taylor.
The other related works implemented fixed-point sine and
cosine functions based on CORDIC and focused on maximum
absolute error or mean square error (MSE). In [16], the
maximum absolute error was 8.04 104 and 5.50 104
for cosine and sine functions with the angles ranging from
/2 to /2 in the step of /500, respectively. Daniel [32]
used 1000 inputs ranging from 0 to /2 to compute the MSE
of sine and cosine and provided MSE= 1.4 1013 .
C. Delay and Area Comparisons
There is a differential on area and delay of designs with dif-
ferent technology generation and design parameters; therefore,
normalized metrics is adopted for the comparisons. To avoid
the effect of technology generation, the comparisons based on
function components are adopted. The function components
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM
TABLE III
D ELAY AND A REA C OMPARISONS
in the compared references are synthesized with the same
constraints. Table 2 is reasonably assumed according to the
results of synthesis. The unit delay and area are set to a full-
adder delay and area, which are denoted by TF A and A F A ,
respectively. To avoid the effect of parameters, the bit-width
of operands and the number of iterations in the compared
CORDIC methods are unified with 64.
The area and delay for look-up table (2 f 2 n) are
2 2n/8 0.5 A F A and log2 f TF A /2, respectively [18].
f
Rotation angle look-up table0 (24 n) is in Z path of our
structures. Scale factor look-up table1 (9 8n/161 n)
provides initial values in K path of Rohit [16]. Initial iteration
value look-up table2 (2n/81 2 n) is in both Tsos [18] and
our structures, replacing the first n/8 1 iterations in X and Y
paths. Scale factor look-up table3 (3n/12+1 n) provides
initial values in K path of Antelo [22].
According to the above estimations and calculations in
Table 2 and last paragraph, different CMOS processes are
taken into consideration for fair comparison. The delay and
area of our TCORDIC, polynomial approximation method, and
various CORDIC methods are compared in Table 3.
Polynomial approximation converges quickly for small vari-
able, but slowly for larger variable. So, in high precision
arithmetic, even though the factorials can be tabulated, this
approach still requires many multiplications and additions [4].
In Florents polynomial-based architectures [34], the coef-
ficient sizes of the polynomials have been optimized to
achieve the minimum overhead. The computation cosine or
sine alone requires 38 block RAMs (18K bits), 15 DSP blocks
(18 18-bit), and 672 slices on Virtex IV, and the area has been
roughly transformed in Table 3. Apparently, the equivalent
area is larger than CORDIC methods, because polynomial
approximation method requires a great mass of DSP blocks
and memory blocks to implement multiplications and look-up
tables.
Actually, the main overhead of our TCORDIC is CORDIC
path. In iterative structure, the truncated multiplier multiplex-
ing calculates the expansion items for Taylor during the com-
pressive iterations for CORDIC, without increasing the area or
affecting the delay. In pipelined structure, Taylor path requires
three truncated multipliers based on booth encoding and CSA.
This involves additional area of 3 M2 /2 M2 /2 A F A +
3 Aboot h , and it is only 1776 A F A with M2 = 32. Besides, the
901
Fig. 12. Delay of various CORDIC methods.
Fig. 13. Area of various CORDIC methods.
truncated multipliers are not in critical path. Therefore, the
following paragraphs focus on the performance analysis of our
implementations compared with various CORDIC methods.
Furthermore, considering Treg = 0.5TF A and Areg =
0.62 A F A [24], the delay and area of various CORDIC methods
are summarized in the units of TF A and A F A , respectively, as
shown in Figs. 12 and 13.
1) Comparisons of Pipelined Structure: In traditional
CORDIC [12], the area and delay are much greater than those
of other designs because of the large number of iterations and
the use of CLA.
Rohit [16] proposes Hybrid algorithm of double step
branching CORDIC [17] and high performance radix-4
CORDIC [22] for which the scale factor compensation is
performed based on the algorithm presented in [23], reducing
the number of iterations to 3n/8 + 1. However, scale factor
look-up table1 occupies 18432 A F A , leading the area of the
structure much larger than those of others. In addition, each
iteration in X and Y paths requires 6 redundant adders, which
increases the cost and delay.
In Tsos Parallel CORDIC [18], the input Z is separated
into L and H , and rotation direction prediction is completed
through MAR and BBR techniques. In X and Y paths, the
first n/8 1 iterations are computed by look-up table2, and
the second phase adopts multi-operand carry-save addition tree
architectures. However, there are 64 operands of 64 bits to be
shifted and compressed in X and Y paths, respectively, which
results in a great area and delay.
In Kuhlmanns literature [19], the directions of all
micro-rotations are precomputed. Despite eliminating the
902 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017
sign examination, the scale factor calculation, and compen-
sation completely, the area is still vast for a large number
of operands to be compressed in X and Y paths. The delay
of the critical path is large because of Tselect ion which refers
to the delay of the selection for the multiple of the shifted
components. In addition, an initial delay of 15.6TF A has to be
added because of the delay of the on-the-fly converter.
Combining the precomputation of all rotation directions
in [19], Lakshmi [21] proposed an architecture using signed
digit arithmetic for rotational Radix-4 CORDIC algorithm. The
delay is larger than ours for the scale factor compensation
and the initial delay of 11.3TF A for the -Prediction block.
In addition, the area is vast for the scale factor calculation and
compensation.
In Antelos mixed Radix-4 and redundant CORDIC [22],
both delay and area are much greater than those of ours. The
delay for Wi+1 , which lies in critical path, is up to 3TF A .
In addition, each of the first n/6 iterations requires a clock
cycle to wait for rotation directions in W path, resulting in a
large latency. In regard to area, it is large owing to the scale
factor look-up table3 and compensation.
In Jaimes enhanced scaling-free CORDIC [24], a specific
booth recoding is used and the corresponding hardware for
Z path can be omitted. Despite the reduction of micro-
rotations, the introduction of traditional CORDIC iterations
and the use of CLA lead to great cost in area and delay.
In our TCORDIC, the delay and area are least among
the comparisons. Rotation direction prediction for n/2 iter-
ations requires only AC S A + 3 At able0 + 2 A64_C L A . Parallel
iterations in the second phase are implemented with two
truncated multipliers, based on booth encoding and CSA.
Calculation Multiplier Z 33 in Z path and booth encoding
require 744 A F A and 336 A F A , respectively. But, the number
of operands for CSA to be compressed is only a quarter of
the number for integrated multipliers, and the bit-width of
operands is optimized further. So, the area for compression
is only one sixteenth of integrated multipliers, and the delay
is reduced by 4TF A .
2) Comparisons of Iterative Structure: In traditional
CORDIC [12], the area is least among the comparisons, but
the delay is unacceptable.
In Hybrid algorithm [16], the area and delay of are large for
scale factor look-up table1 and the large number of redundant
adders.
In Radix-4 CORDIC [22], the area of is 152 A F A less
than that of ours, but the delay is unacceptable. Despite the
zero skipping technique, the average number of iterations is
still 4n/5. The critical path is 6.7TF A in W path, including
1.3TF A for scale factor look-up table3 and 3.5TF A for the
judgement of the skipping.
In our TCORDIC, a 4-stage compressive iteration module
is multiplexed. Only the delay increases for 8TMU X _8 in
critical path, but the area for compressive iterations reduces
to one eighth of that in pipelined structure. A 53 53-bit
truncated multiplier is multiplexed, and parallel iterations can
be completed with an increase of only 3 clock cycles, as
compared to those required for our pipelined structure.
TABLE IV
P OWER AND A CTIVITY WITH D IFFERENT T ESTING S ETS
D. Power Analysis
The power consumption of a digital circuit is a function
of the silicon area given a fixed frequency and operating
voltage [25]. The power consumption for our architecture
and traditional architecture are measured with 1 GHz clock
cycles, 0.9 V supply voltage, and vast of random inputs (SG r )
are used to obtain the power and activity in Table 4.
Compared with traditional CORDIC, TCORDIC can achieve
lower power consumption for pipelined structure. However,
this is reverse for iterative structure. The trend of power
consumption between traditional CORDIC and TCORDIC is
the same with the trend of area as illustrated in Fig. 13.
The area comparisons of the implementations of our
TCORDIC, polynomial approximation method, and various
CORDIC methods have already been provided in Table 3.
According to the relationship between area and power con-
sumption, we can expect that our pipelined architecture will
consume less power than [12], [16], [18], [19], [21], [22],
[24], and [34]. For iterative structure, the power consump-
tion of our TCORDIC is less than [16], and almost the
same as [22].
Table 4 also illustrates that there is no significant change in
the power consumption between TCORDIC, which involves
Taylor algorithm, and our pure CORDIC.
Six testing sets (SG 1 , SG 2 , SG 3 , SG 4 , SG 5 , and SG 6 ) of
vast inputs are applied to evaluate the power consumption of
our designs by SpyGlass. All the inputs of the testing sets
SG 1 and SG 4 satisfy E o f f set E Z N, and Taylor is not
selected. All the inputs of the testing sets SG 2 and SG 5 meet
E o f f set E Z > N, and Taylor is selected. Half of the inputs
of the testing sets SG 3 and SG 6 meet E o f f set E Z > N, and
the possibility of selecting Taylor is 50%.
In iterative structure, the power consumption for TCORDIC
computation is 7.5% greater than that for pure CORDIC
computation. When Taylor is not selected, the inputs
of multiplexing multiplier remain unchanged during the
first 16 clock cycles.
In pipelined structure, the power consumption for
TCORDIC computation is 2.0% greater than that for pure
CORDIC computation. When Taylor is not selected, the inputs
of Taylor path remain unchanged. When Taylor is selected,
only half of the parallel iteration in CORDIC path is used to
calculate, and the other half remain unchanged.
ZHU et al.: LOW LATENCY AND LOW ERROR FLOATING-POINT SINE/COSINE FUNCTION BASED TCORDIC ALGORITHM 903

  i j
VI. C ONCLUSION While m n/2 + 1, i j2 (2(n+2)
2 (3n/2) ) + (2 (n+4) 2 (3n/2+1) ) + +(2(2n4)
In this paper, TCORDIC algorithm, which combines low (2n3)
latency CORDIC and Taylor algorithm, is presented to 2 ).     i j kl
2) The computation of l2 :
improve the accuracy of floating-point sine/cosine computa-     i j kl i j k
4
tion, and guarantee the accuracy within one ulp even when the i j k l2 involves in Cnm terms to
input is close to 0 or /2. Several schemes, sign prediction, be accumulated.
parallel iteration, and truncated multiplier, are employed to With m n/2 + 1, the maximum value of Cnm 4 is
(n/21)(n/22)(n/23)(n/24)
reduce the delay for low latency CORDIC. Finally, taking 4! , and the maximum value of
IEEE-754 double precision floating-point sine and cosine 2i j kl is 2(n/2+1+n/2+2+n/2+3+n/2+4) .
functions as an example, iterative and pipelined structures are Considering the function f (n) = 2n/8+4 n, f  (n) =
implemented, and the advantages of low latency and low error 2n/8+4 ln 2 18 1 > 0 when n 0.
are achieved. With n = 0, f (0) = 20/8+4 0 > 0.
When n 0, 2n/8+4 n
< 1, and ( 2n/8+4
n
)4 < 1.
A PPENDIX A    
P ROOF OF THE S IMPLIFICATION OF E QUATION (8) 2i j kl
i j k l
When m n/2 + 1, equation (8) can be simplified from (n/2 1)(n/2 2)(n/2 3)(n/2 4) 2n10
equation (7) with the error of X n or Yn less than 2n , and 2
4!
following is the proof of the simplification. The proof can be (n/2 1)(n/2 2)(n/2 3)(n/2 4) 3n/2
completed by three steps. = 2
4! 2n/2+10
Step one: the computation of the omitted value in Am,n .
Am,n = 1 + A , where A is the omitted value. n4 n
< 23n/2 = 23n/2 ( )4 < 23n/2 .
  2n/2+16 2n/8+4
A = i j 2i j   i(1)..i(2t ) for
i(1) ..
i j
    3) The computation of i(2t ) 2
i j k l 2i j kl t 3:
i j k l
  Considering the function g(n) = 2n/6+2 n, g  (n) =
+.. (1)t .. i(1) ..i(2t ) 2i(1)..i(2t ) 2n/6+2 ln 2 16 1 > 0 when n 7.
i(1) i(2t )
  With n = 7, g(7) = 27/6+2 7 > 0.
| i j 2i j |
i
   
j n
Therefore, 2n/6+2 < 1 when n 7.
+| i j k l 2i j kl | With (n/2 1)/2 (n m)/2 t 3,
i j k l
   
+.. + |(1)t .. i(1) ..i(2t ) 2i(1)..i(2t ) | .. 2i(1)..i(2t )
i(1) i(2t ) i(1) i(2t )
     
2i j + 2i j kl (n/2 1)(n/2 2) (n/2 2t) t n
i j i j k l 2 2t
  (2t)!
+.. + .. 2i(1)..i(2t ) .
i(1) i(2t ) (n/2 1)(n/2 2) (n/2 2t)
= 22n 
The following
 sub-items 1), 2), and 3) aim to calculate (2t)! 2(t 2)n+ 2t
.. 2 i(1)..i(2t ) for t = 1, t = 2, and t 3,
i(1) i(2t ) n 2t n 2t
respectively. < 22n  < 22n
  (2t)! 2(t 2)n+ 2t +2t 2(t 2)n+4t
1) The computation of i j 2i j :
  i j n n
With m 1 < i < j < n, i j2 consists = 22n ( (1/21/t )n+2 )2t < 22n ( n/6+2 )2t < 22n
2 2 2
of Cnm terms to be accumulated when the iteration      
i j
formulas between the m t h and the (n1)t h are expanded. A 2 + 2i j kl
i j i j k l
a) With i = m and j = m + 1, m + 2, , n 1,  
 m j = 22m 2(m+n1) . + .. + .. 2i(1)..i(2t )
j 2 i(1) i(2t )
With i = m + 1 and j = m + 2, m + 3, , n 1,
b)  (n+2) (3n/2)
m1 j = 22m2 2(m+n) . < {(2 2 ) + (2(n+4) 2(3n/2+1) )
j2
c) With i = m, i = m + 1, , i = n 2, + +(2(2n4) 2(2n3) )} + (23n/2 )
 
2i j + ((n/2 1)/2 2)(22n )
i j
  < (2(n+2) + 2(n+4) + +2(2n4) )
= 2m j + 2m1 j
j j
 + {(23n/2 ) + ((n/2 1)/2 2)(22n )
++ 2(n2) j
j
2(3n/2) 2(3n/2+1) 2(2n3) }
2m (m+n1) 2m2 (m+n)
= (2 2 ) + (2 2 )
< 2(n+2) + 2(n+4) + +2(2n4) < 2n1 .
+ +(2(2n4) 2(2n3) ).
904 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 4, APRIL 2017

Therefore, except the first item 1, the maximum sum of R EFERENCES

other items in Am,n is less than 2n1 .
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Baozhou Zhu was born in 1992. He received
the B.S. degree in mechanical engineering and
automation from South China University of Tech-
nology in 2015. He is currently working toward
the M.S. degree in the field of microelectronics
and solid-state electronics at the National University
of Defense and Technology (NUDT), China. His
research interests include high performance com-
puter architecture and computing engineering.
905
Yuanwu Lei was born in 1982. He received the
M.S. degree and the Ph.D. degree in computer
science from National University of Defense and
Technology (NUDT), China, in 2007 and 2012,
respectively. His research interests include high
performance computer architecture and computing
engineering.
Yuanxi Peng was born in 1966. He received the
B.S. degree in computer science from Sichuan
University, China, in 1988 and the M.S. and
Ph.D. degrees in computer science from National
University of Defense and Technology (NUDT),
China, in 1998 and 2001, respectively. He was
a Visiting Professor in Department of Electronic
and Computer Engineering, University of Toronto,
Canada, during 20102011. He has been a Professor
of Computer School in NUDT since 2011. His
research interests are in the areas of high perfor-
mance computing, multi- and many-core architectures, on-chip networks,
cache coherence protocols, and architectural support for parallel programming.
Tingting He was born in 1991. She received the
B.S. degree in information systems and informa-
tion management in Jiangsu University of Science
and Technology, China, in 2013. She is currently
working toward the M.S. degree in microelectronics
and solid-state electronics at the National University
of Defense and Technology (NUDT), China. Her
research interests include high performance com-
puter architecture and computing engineering.