High Electron Mobility Transistors (HEMTs)

Source Gate Drain

Wg 1000 VG = 2 V
VG = 1 V
800

ID (mA/mm)
Active Region 600
gm = 200 mS/mm
S. I. Buffer
d
400
Open channel 200
Lg
0
Source Gate Drain
Wg 0 2 4 6 8 10 12 14 16
VDS (V)

Active Region

S. I. Buffer

Pinch off
Lg
Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics
of Semiconductor Devices
 Output Power Calculation (AC, not DC)
A
I max
linear VSWING ISWING
IDS BIAS POINT Pout, max =
8
Q I SWING
Minimize Vknee
B
Maximize Vbreakdown
V
knee VDS
Vbreakdown
Maximize Imax

VSWING Maximize ns or nsvs

GaAs pHEMT AlGaN/GaN HEMT

Vknee (V) 1 5 (~ Vpinchoff)

Vbreakdown (V) 20 100 (over 200 reported for

small Lgd)
Imax (A/mm) 0.6 1.2 (over 2 reported)

Pout, max (W/mm) 1.4 14 (32 highest reported)

 Sample power calculations
Let Vknee be 4 V, and Vbd be 120 V, and Iswing be 120 mA for a 100
micron gate width device. Calculate the maximum output power in
dBm and in W/mm
Solution: Total maximum output power = 1/8 (120 4) 120 mW
= 1740 mW. So output power in dBm = 10 log1740 = 32.405
dBm. Output power density is 1740 mW/100 micron = 17400
mW/mm = 17.4 W/mm.
If the gain is 15 dB, what is the input power?
Solution: 10 log (Pout/Pin) = 15 Pout = Pin x 101.5 = Pin x 31.62
Pin = 17.4/31.62 = 0.5502 W/mm.
If the dc input power is also given then the Power-Added
Efficiency (PAE) can be calculated as (Pout Pin)/Pdc

Slide # 3
 Performance criteria for microwave transistors
Output Power: Total microwave power available (W/mm)
Gain: G = Pout/Pin, log G = Log Pout Log Pin (Gain usually
measured in dB, but Pin and Pout are in dBm)
Ft : Maximum frequency of oscillation or the frequency at which
the short circuit current gain is 1
Fmax: The frequency at which the power gain is 1 for a perfectly
matched load
Power added efficiency (P.A.E): (Pout Pin)/Pdc, Pin = input
microwave power, Pdc = total dc power in at the gate and drain
terminals.
Linearity: The measure of gain against input signal level. High
linearity means lower harmonic content in the output signal
Noise Figure: SNRin/SNRout (usually expressed in dBm by taking
the log)
Stability: long term and short term operational stability

Slide # 4
 AlGaN/GaN HEMT: wish list
High VBr
Minimize
Buffer leakage: GaN:Fe
Gate leakage: Insulated-gate
Other device structures to improve VBr

High power efficiency

When efficiency is low

Power dissipation at semiconductor devices

Ron
efficiency

How to maximize efficiency

Eliminate surface traps (passivation/epitaxial solutions)
Eliminate bulk traps (growth condition tuning)
Decrease leakage (low dislocation density/insulators?)

Slide # 5
 Growth Challenge I: heteroepitaxy
Tiny changes in growth conditions
have strong effect on GaN properties
(T,d, V/III)

+ very sensitive coalescence process

= process much less robust than

homo-epitaxy

Lattice mismatch

High dislocation density in epitaxial

layers and at the interface of the
time heteroepitaxial layers.

Slide # 6
 Growth Challenges II: alloy epitaxy
GaN technology still less mature than GaAs and InP technology

Crystal growth is dominantly heteroepitaxial

Alloys:
todays high efficiency devices
AlN InN
AlxGa1-xN xAl < 0.4
InxGa1-xN xIn < 0.4

High Al (x=0.5 ~ 1) is currently under intense

research (UV LEDs and detectors etc.)
GaN
Alloys with high Al and/or In compositions

difficulties related to interplay of

Material properties and
Epitaxy process

Stacia Keller et al. UCSB

Slide # 7
AlGaN/GaN high electron mobility transistor: basics
Donor-like surface
Polarization charge traps (empty)
Unlike AlGaAs/GaAs HEMT
requiring intentional doping to
Gate
form charge, 2DEG in
_ __ _ _ __ _ _ __
_ _ _ _
_ __ _
_
AlGaN/GaN HEMT are Source AlxGa1-xN Drain
P
polarization-induced. No
_ +_ +_+ _+ _+ +_ +_+_+ _+ +
_ +_ +_+ _+ _+ +_ +_+_+ _+ +
_ +_ +_
intentionally doping is needed.

Channel 2-DEG GaN

Electrons come from surface
states.

-
2DEG +-
+- +
+- +
+ - +- UID --
+ -- Surface +- AlGaN +
--
+ + 2DEG
states - + -
Donors
+
Polarization +
charge
AlGaAs/GaAs HEMT AlGaN/GaN HEMT
Slide # 8
 AlGaN/GaN HEMTs: Formation of the 2DEG
Layer structure Schematic band diagram
20-30 nm Al0.3Ga0.7 N
B AlGaN GaN Ec
2DEG
Ec
GaN buffer(1-2 m) EF
d

+ve comp
Nucleation layer (~ 20 nm) B

Sapphire/SiC substrate
2 DEG
surf
+ B 0
ns = 2 [ B + E F (ns ) Ec ]
e de
The 2DEG is an explicit function of the surface barrier, AlGaN
thickness, and the bound positive charge at the interface
Slide # 9
 Comparison with GaAs HEMT Physics
Schematic band diagram AlGaAs/GaAs HEMT
B AlGaN GaN
Ec
Ec
EF
d

comp AlGaAs
+ve
B donor
GaAs buffer
layer

2 DEG
surf
AlGaAs spacer

No doping is required for the 2DEG to be present at the interface.

Higher sheet charge and higher conduction band discontinuity for
AlGaN/GaN heterostructure
Slide # 10
 Heart of HEMT: 2DEG
for high power, high frequency HEMTs:

high xAl,
coherently strained,
trap free AlGaN/GaN heterojuction,
(abrupt + smooth on an atomic level)
carrier confinement,
high breakdown voltage,
high currents
AlGaN u.i.d.
AlGaN:Si ?
2DEG
(density and mobility)
GaN S.I.
Determined by
- xAl
- interface roughness
Al2O3/SiC - alloy scattering
- dislocation, etc.
Ambacher et al, JAP 87(1) 2000
Slide # 11
 Properties of the 2DEG
2DEG Mobility vs. density

Spacer layer
thickness vs.
2DEG density
and mobility

dspacer depends on
intended application

For AlGaAs/GaAs heterostructures, the spacer layer

thickness is important for 2DEG mobility and density
The 2DEG does not freeze out at very low temperature
unlike the 3D doping
The 2DEG mobility does not decrease with decrease in
temperature unlike the 3D case
The 2DEG mobility can increase with increase in 2DEG
density due to increased screening unlike the 3D doping
Slide # 12
 2DEG Influence of the Al-composition

xAl>0.2:  300K ~ 1/xAl

MOCVD
1500 xAl : - interface problems
[cm / Vs]

1400 - strain induced defects

2

1300 - higher impurity incorporation

1200 - alloy ordering/clustering
1100
300

1000  ns ~ xAl

[10 cm ]
1.8

-2
- charge increases due to
1.6
1.4 spontaneous polarization and

13
1.2 piezoelectric effects
0 1.0
0.8 xAl<0.2:  300K ~ xAl
0.6 ns
0.0 0.2 0.4 0.6 - better confinement of the 2DEG
xAl at higher xAl

- low xAl = low ns: less efficient

screening of defects
relaxed

Slide # 13
 Temperature dependence of v-F curve
3 3

Electron Velocity (107 cm/s)

GaAs
Electron Velocity (107 cm/s)

GaN 300 K 300 K

500 K
500 K
700 K 700 K
2 2

1 1

0 0
0 200 400 600 0 4 8 12 16 20
Electric Field (kV/cm) Electric Field (kV/cm)

Usually the regions are separated into regions of constant and zero
mobility
A velocity overshoot is expected for GaN similar to GaAs case, but
usually not seen, possibly due to high background doping
At higher temperature, the degradation of v-F curve for GaN is
much smaller than GaAs
Slide # 14
 Temperature dependent mobility

Increasing alloy composition in barrier

Debdeep Jena Ph.D dissertation Slide # 15

 Electron transport

 Phonon scattering:
---most important at room temperature

 Alloy disorder scattering

---potential disorder from ternary alloy
---important at low and room
temperature

 Surface roughness scattering

---important at low temperature

 Ionized impurities scattering

 Dislocation scattering
 Dipole scattering
1 1
Mattheissen rule for total mobility: =
net i i
where i refers to the mobility corresponding to different sources
Alloy disorder scattering is the limiting factor at low temperature.
Alloy disorder scattering also plays an important role at room temperature when carrier
concentration is high.
It is due to the ternary nature of AlGaN.
Debdeep Jena Ph.D dissertation
Slide # 16
 Methods for reducing scattering
Controllable scattering mechanisms
Background impurity scattering: By growing the
material purer
Alloy scattering: By putting a thin binary alloy
(AlN) at the interface
Dislocation scattering: By growing on lattice and
thermally matched substrate
Interface roughness scattering: By growing very
smooth interfacial layers
Rest of the scattering processes are usually
physics limited
Slide # 17
 2DEG High-mobility AlN interlayers

30 2.5
AlGaN/GaN AlGaN/GaN

Mobility (10 , cm /Vs)

25 2
AlGaN/AlN/GaN AlGaN/AlN/GaN
cm )

2
-2

AlGaN 20
1.5

4
1 nm AlN
12

15
(10

S.I. GaN 1
10
S
N

5 0.5
T = 17 K
T = 17 K
sapphire
0 0
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Al mole fraction x Alloy composition x
dAlN = 1 nm
by MBE, I.P. Smorchkova et al., J. Appl. Phys. 90 (2001) 5196

Similar results obtained by MOCVD

no alloy scattering
Slide # 18
 AlN as a barrier layer
0.08 6
Al0.22Ga0.78N/GaN

2DEG density (10 cm )

AlN/GaN

-2
5
0.06

13
AlGaN/GaN 4
Probability

interface
0.04
3

0.02 2

1
0.00
0
24 26 28 30 32 34 36 0 5 10 15 20 25 30
Distance (nm) AlN barrier thickness (nm)

Simulations

Alloy disorder scattering: Use AlN as barrier material

---No alloy disorder scattering:
---Wavefunction penetration higher mobility
---Ternary material: AlGaN
---Higher polarization charge density:
Reduce alloy scattering: higher carrier concentration
---Increase Al composition
---Binary material: AlN However, after gate metal deposition, it was
found to be almost ohmic due to tunneling!
Slide # 19
 AlGaN/AlN/GaN Heterostructure

Incorporation of a thin AlN (<1nm)

25 nm Al0.3GaN into a standard AlGaN/GaN HEMT

0.7-1 nm AlN The thickness of AlN interfacial

layer is below critical thickness for
formation of 2DEG. The main
UID GaN
purpose is to improve mobility.

Thin AlN layer forms a larger

SiC Substrate effective Ec, which affects both
mobility and carrier concentration.

Slide # 20
 Charge and mobility vs. AlN thickness
AlGaN/AlN/GaN HEMT
1600
Charge(Simulation)
1.8 Charge(Experiment)

2DEG Density (10 cm-2)

Mobility(Experiment) 1400

Mobility (cm V s )
-1
13
1.6

-1
1200

2
1.4
1000

1.2 optimum 800

thickness
1.0 600
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Thickness of AlN (nm)

 Theory predicts that ns increases with AlN thickness

 In real growth, thick AlN suffers by the relaxation. Above
0.5nm, charge saturates and mobility drops

Slide # 21
 Band Diagram
25 nm Al0.33Ga0.67N/ 1 nm AlN/GaN HEMT 25 nm Al0.33Ga0.67N/GaN HEMT
3 3
Thin AlN

2 - 2
- + AlGaN GaN
Energy (eV)

Energy (eV)
- + Effective EC
1 - +
+ 1

0
0
EC

-1
0 10 20 30 40 50
0 10 20 30 40 50
Thickness (nm)
Thickness (nm)
0 0 0 0
AlGaN t AlGaN B + 2
Ec' ,eff AlGaN t AlGaN B + 2
EC, AlGaN
q q q q
ns = ns =
t AlGaN + t AlN + d 0 t AlGaN + d0
' q2
E c , eff = EC , AlGaN + AlN t AlN
0
Slide # 22
 Hall data and DC I-V

Hall Data:
1000 VG = 2 V
 Conventional undoped AlGaN/GaN VG = 1 V
ns = 1.1 1013 cm-2 800
= 1200 cm2/V s

ID (mA/mm)
600
gm = 200 mS/mm
 Undoped AlGaN/AlN/GaN:
400
ns = 1.22 1013 cm-2
= 1520 cm2/V s 200

 Si-doped AlGaN /AlN/GaN: 0

ns = 1.48 1013 cm-2 0 2 4 6 8 10 12 14 16
= 1500 cm2/V s
VDS (V)

 Mobility was improved with a slight increase of 2DEG

 Si doping increased 2DEG density while retaining high
mobility
Slide # 23
 Power Performance
Undoped AlGaN Si-doped AlGaN
35 40 35 40
8.1 W/mm
Pout 35 Pout 8.47 W/mm
30 Gain 30 Gain
35
Pout (dBm), Gain (dB)

Pout (dBm), Gain (dB)

PAE 30 PAE 30
25 25
25 25

PAE (%)

PAE (%)
20 20
20 20
15 15
15 15
10 10
10 10
5 5 5 5
0 0 0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Pin (dBm) Pin (dBm)

On SiC substrate. SiN passivated.

8.1W/mm with a peak PAE of 23% was obtained at 8GHz at VD=50V,
ID=130mA/mm from an undoped AlGaN barrier HEMT.
8.47W/mm with a PAE of 41% was obtained at 10GHz at 8GHz at VD=45V,
ID=160mA/mm from a Si-doped barrier HEMT.

Slide # 24
 Effect of Si doping density
Nd/Polarization=1.2 Nd/Polarization=0.8 Nd/Polarization=0.5

Electron, Hole Concentration (10 cm )

-3
8
4

18
6
2
Energy (eV)

4
0

-2 parallel conduction 2

holes
-4 0

0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350
Thickness (nm) Thickness (nm) Thickness (nm)

ns = 1.7 1013 cm-2 ns = 1.36 1013 cm-2 ns = 1.04 1013 cm-2

npara = 0.3 1013 cm-2 ps = 0.18 1013 cm-2

Too much Si doping results in free electrons in graded layer,

leading to parallel conduction
Too little Si doping is not enough to remove holes
~80% compensation puts fermi level in the middle of bandgap
Slide # 25
 Design rules for AlGaN/GaN HEMTs:
Materials perspective
Thickness of the barrier layer: affects 2DEG
concentration and vertical gate field (which controls gate
leakage current, VD, breakdown, and can also affect device
degradation)
Al composition of the barrier layer: affects 2DEG
concentration and EC, which confines the 2DEG
Nucleation and buffer layer: affects dislocation density,
and surface morphology (both affect mobility, one by
charged line scattering and other by interface roughness
scattering) and parasitic conduction.
Substrate for epitaxial growth: affects the heat
conductivity and ultimate output power performance as
well as defect density, and parasitics.
Slide # 26
 Transistor fabrication layout
Submicron Ni/Au Air-bridge to connect
4 isolated source pads
mushroom gate 3
defined by e-beam
Cl2 based ECR
1
Ti/Al/Ti/Au ohmic mesa isolation
contact annealed at 2
800C (0.3 to 0.6 -mm)
SEM photo showing air-bridge
SEM image of a submicron mushroom gate over the gate metal (T-layout)

Slide # 27
 Design rules for AlGaN/GaN HEMTs:
Fabrication perspective
2 x 125 m U-gate 2 x 75 m T-gate
D D
S S
S S
G
G

The gate footprint and the cross-sectional area and width controls the frequency
response
Lg lower means fT goes up
Cross-section and gate width control gate resistance (this is why mushroom gates are
used)
The gate drain spacing as well as gate footprint determines the breakdown voltage
Lg lower means VBR down
Gate-drain spacing up means VBR up
The geometry of the device also plays a role
The U-geometry device has 10 15 % lower gm, Idss due to self heating
Slide # 28
 Large periphery devices
Parallel fingers or fishbone layout for 12 x 125 m devices:
Parallel fingers Fishbone

Air bridges
Larger periphery devices used for higher actual output power NOT
power density (usually more than 1 mm gate finger width)
The fabrication processes are complicated as this involves air-
bridging the source or the drain.
Large periphery design issues: electrical and thermal
Slide # 29
 Design issues for large periphery devices
 Electrical issues:
The voltage drop along the gate length causes lower PAE
Phase difference at the gate fingers reduce overall PAE
Finite Ron reduces PAE. This becomes severe in presence of
trapping as Ron increases
 Thermal issues:
Device heating is a problem at higher output power, since
power wasted is also larger
The maximum possible output power depends on the
conductivity of the substrates. SiC substrates are commonly
used. Thinned sapphire substrates have also been used.
The number of gate fingers as well as the gate finger pitch
determine the maximum temperature rise in a device.
Slide # 30
 DC characteristics of AlGaN/GaN HEMTs
10.3100 m devices (~35% Al)

The negative slope in the dc characteristics of sapphire is either

due to heating or trapping
The dc characteristics are better for HEMTs fabricated on SiC
than on sapphire possibly because of reduced dislocation density
and increased thermal conductivity
The difference becomes more severe with scaling
Slide # 31
 RF performance
Small signal Large signal
30 60
30 h21 3.4W/mm
Pout

Pout (dBm), Gain (dB)

UPG 25 Gain 50
h21, UPG (dB)

PAE
20 40

PAE (%)
20
30
15
20
10 10
10
5
0 0
0 5 10 15 20 25
1 10 100
Pin (dBm)
f (GHz)

ft of 22GHz and fmax of 40GHz were On sapphire substrate.

obtained from a 0.7um-gate-length No SiN passivation.
HEMT at drain bias of 10V and drain 3.4W/mm with peak PAE 32% was
current of 240mA/mm. obtained at 10GHz when VD=15V and
ID=230mA/mm.

Slide # 32
 RF performance

Small signal Large signal

35 12W/mm
Pout 50

Pout (dBm), Gain (dB)

h21
40 Gain
UPG 30
PAE 40
h21, UPG (dB)

30

PAE (%)
25 44%
30
20 20
20
15
10
10
10
0 0
1 10 100 0 5 10 15 20
Frequency (GHz) Pin (dBm)

ft of 21GHz and fmax of 39GHz were On SiC substrate

obtained from a 0.7um-gate-length 12W/mm with a peak PAE of 44% was
HEMT at drain bias of 15V and drain obtained at 4GHz at VD=50V,
current of 280mA/mm. ID=270mA/mm

Slide # 33