Negative Bias Temperature

Instability (NBTI)
Physics, Materials, Process,
and Circuit Issues

Dieter K. Schroder
Arizona State University
Tempe, AZ
 Introduction
What is NBTI?
Material Issues
Device Issues
Circuit Issues
Effect of
Hydrogen
Nitrogen
Water
Fluorine
Deuterium
Boron
Stress
NBTI Minimization
 What Is NBTI?
Negative bias temperature instability occurs mainly in
p-channel MOS devices
Either negative gate voltages or elevated temperatures
can produce NBTI, but a stronger and faster effect is
produced by their combined action
Oxide electric fields typically below 6 MV/cm
Stress temperatures: 100 - 250C
Drain current, transconductance, and
off current decrease
107
Absolute threshold voltage
increase

Eox (V/cm)
Such fields and temperatures
are typically encountered 106
during burn in, but are also
approached in high-performance
ICs during routine operation 105
1970 1980 1990 2000
Year
 Parametric Impact
Material
Interface traps, Dit
Oxide charges, Not
Device
Threshold voltage, VT
Transconductance, gm
Subthreshold slope, S
Mobility, eff
Drain current, ID,lin, ID,sat
Circuit
Gate-to-drain capacitance, Cgd
Delay time, td
 Device Lifetime Limits
NBTI key reliability issue

3
T=100oC
SIA
Hot Carrier Limit Roadmap
VDD (V)
Region
2

NBTI Limit
Region
1
2 2.5 3 3.5 4 4.5 5
Oxide Thickness (nm)

N. Kimizuka et al., IEEE VLSI Symp. 73 (1999)

 MOSFET Performance
MOSFET drain current depends on
Dimensions: W, L, Cox ~ 1/tox
Mobility: eff
Voltages: VG, VD, VT

ID = (W / 2L)eff Cox (VG VT )2

Delay time: td
CVDD C
td = =
ID (W / 2L)eff CoxVDD (1 VT / VDD )2

ID and td if VT and eff

When device parameter change
exceeds a certain value failure
 Earliest NBTI
Generation of fixed charge and interface states
with negative gate bias was observed very early
during MOS development in 1967!
3 1012
T=300oC
(Qf+Qit)/q (cm-2)

tox=200 nm (111)
(100)
2 1012 (111)
(100)

1 1012

0
0 100 -1 106 -2 106 -3 106
Electric Field (V/cm)
B.E. Deal et al., J. Electrochem. Soc. 114, 266 (1967)
 Typical NBTI Features
Interface traps, Dit, and positive oxide charges,
Not, are generated at similar rates
Dit Not

10 10

Dit (cm-2eV-1)
Not (cm-2)

1 1
Dit
Not
0.1 0.1
100 101 102 103 104
Stress Time (s)
 VT, Transconductance
Charge pumping current Icp ~ interface state
density Dit
Transconductance gm ~ effective mobility eff ~ Dit
103 102
VT (mV); Icp (pA)

gm/gmo
VG=-8 V VG=-2.3 V, T=100oC
101
102 Icp
VT
100

VT (mV); -
101
VT 10-1
gm/gmo
100
W/L = 10 m/2 m 10-2
tox=15 nm, T=135oC L=0.1 m, tox=2.2 nm
-

10-1 10-3
101 102 103 104 105 - 100 101 102 103 104
Stress Time (s) Stress Time (s)
C. Schlnder et al. Microelectron. N. Kimizuka et al., IEEE
Rel. 39, 821 (1999) VLSI Symp. 92 (2000)
 Threshold Voltage
Threshold voltage of p-channel MOSFETs
decreases with stress time. Why?
Qox Qit QS
VT = MS + 2F +
Cox Cox Cox
10
W/L = 10 m/2 m
8 tox=15 nm, T=135oC
VT (mV)

4
-

2
VG=-8 V
0
10-3 10-2 10-1 100 101
Stress Time (h)
C. Schlnder et al. Microelectron. Rel. 39, 821 (1999)
 SiO2 and SiO2/Si Interface
Si, Si/SiO2 interface, SiO2 bulk, and oxide defect
structure

A: Si-Si Bond
(Oxygen Vacancy)
B: Dangling Bond
D
C: Si-H Bond
Hydrogen C This looks
D: Si-OH Bond
really messy!
A
Oxygen
B
+
+

+
+

Dangling Bond (Dit)

Si
Interface Traps
Si has 4 electrons
At the surface, Si atoms are
missing: Dit ~ 1014 cm-2eV-1
After oxidation: Dit ~ 1012 cm-2eV-1
After forming gas (H2/N2) anneal:
Dit ~ 1010 cm-2eV-1
Dit are energy levels in the band
gap at the Si surface
Hydrogen is very important?
 NBTI Mechanism
A hole (h) is attracted to the Si/SiO2 interface
It weakens the Si-H bond until it breaks
The hydrogen (H) diffuses into the oxide or Si
substrate
If H diffuses into the Si, it can passivate boron ions
Leaves an interface trap (Dit)
 Holes Are The Problem !
Electromigration Chip Delamination
Via Electromigration

P. Nguyen, ASU
10 m

Cut Voids
= 38 h T.S. Sriram and E. Piccioli
W plug Compaq L. Wagner, IRPS 2004

Flip Chip Voiding

10 m

G. Dixit, IRPS 2004

Solder Bump EM
p+ p+
L. Wagner, IRPS 2004
n-type
40 m J= 2.25x104 A/cm2

K. Tu, UCLA
 Interface Trap Charge
Band diagrams of the Si substrate of a p-channel MOS
device shows the occupancy of interface traps and the
various charge polarities for an n-substrate
Acceptor with electron: negative charge
Donor without electron: positive charge
(a) negative interface trap charge at flat band
(b) positive interface trap charge at inversion
(Heavy line: interface trap occupied by an electron;
light line: unoccupied by an electron)

"0"
Dit
EC EC
"0" "+"
Acceptors EF EF
"-" "0"
Ei Ei
Donors "0"
EV EV
(a) (b)
 Threshold Voltage
Nit and Nf 1010 cm-2; 0.1 m x 1.0 m gate (A = 10-9 cm2),
there only 10 interface traps and 10 fixed oxide charges at
the SiO2/Si interface under the gate VT
Qit + Qf 20q 1.6 x 10 19 x 20
VT = = tox = t = 9.2 x 103 tox
Cox Kox o A 13
3.45 x 10 x 10 9 ox

For tox = 5 nm VT -5 mV. For VT = -50 mV, device

failure Nit = Nf = 1011 cm-2
Suppose that in a matched analog circuit, one MOSFET
experiences VT -10 mV and the other VT -25 mV. This
15 mV mismatch in a VT = -0.3 V technology 5%
mismatch. High performance analog transistor pairs that
require mismatch tolerances of 0.1% to 0.01%.
 Reaction Diffusion Model
Holes interact with Si-H bond
Holes weaken Si-H bond
At elevated temperature, the Si-H bonds dissociate
Si 3 SiH + h + Si 3 Si + H +

Initially
Dit generation ~ Si-H dissociation rate (reaction limited)
Later
Dit generation ~ hydrogen diffusion rate (diffusion limited)

M.A. Alam, IEDM, 2003; IRPS 2005

 Reaction Diffusion Model
dNit
= k f (NSi H Nit ) k r Nit NH ( x = 0)
dt
Reaction
H-Si

Threshold Voltage
-VG H -Si n-Si
H-Si

Diffusion
H-Si
-VG H -Si n-Si
H -Si

H-Si
0 H -Si n-Si Time
H -Si
 Hydrogen Model
Hydrogen from Si substrate drifts to SiO2/Si
interface
Ho near/at SiO2/Si interface traps a hole H+
H+ depassivates Si-H bond Dit and H2
Si 3 SiH + H + Si 3 Si + H2
Some H+ drifts into SiO2 Not

D.M. Fleetwood et al. Appl. Phys. Lett. 86, 142103 (2005)

 Device Dependence
Weff Cox / L
I D ,lin = (VG VT VD / 2)VD
1 + VD / lat L
ID ,lin VT
=
ID ,lin VG VT

(VG VT )2
I D ,sat = Wv satCox Wv satCox (VG VT )n
VG VT + sat L
ID ,sat VT
= n
I D ,sat VG VT

L dependence
Long channel: n 2, short channel: n 1
Hence long channel degradation worse
ID dependence
ID,sat worse than ID,lin due to n
 Device Dependence
tox dependence
With scaling, tox and VG-VT (headroom)
Hence thin oxide degradation worse for same VT

eff dependence qDit qDit

Cit = qDit VT = = tox
Cox K ox o
For same VT, as tox Dit , eff
Hence mobility degradation worse for thin oxides
 How Can This Be ?
The lower picture is after the parts are moved
Where does the missing hole come from?
 Effect on Circuits
Inverter Vin Vout n-MOS p-MOS
Bias Stress Stress
1 VDD 0V PBTI Off State
2 0V VDD Off State NBTI
VDD p-MOS
NBTI

Vin Vout V(t)

Vin(t) Vout(t)

VSS
Time
CMOS Inverter Degradation
p-MOS NBTI degradation
is dominant degradation
mechanism during static
inverter stress
|VG |= 2.8 V
p-MOS NBTI
10

n-MOS Off State

VT (mV)
1
n-MOS PBTI

-
p-MOS Off State

T=105oC
0.1
0 1000 2000 3000 4000 5000
Stress Time (s)
V. Reddy et al. IEEE 40th Ann.
Int. Rel. Symp., 248 (2002)
 Effect on Circuits
Occurs primarily in p-channel MOSFETs with
negative gate voltage bias and is negligible for
positive gate voltage
In MOS circuits, it occurs most commonly
during the high state of p-channel MOSFETs
inverter operation
Leads to timing shifts and potential circuit
failure due to increased spreads in signal
arrival in logic circuits
Asymmetric degradation in timing paths can
lead to non-functionality of sensitive logic
circuits product field failures
 Circuit Dependence
td dependence
Headroom Degradation
CVDD t d VT

Drain Current Shift

td = =n Limited Limited
ID td VG VT (VG - VT)-1 (VT)
t d Kt 0.25 Eox
= Eox exp
td VG VT E0
Circuit delay degrades
with VT increase
ISCAS C423: 10% after 10 yrs*
Operating Voltage
CGD dependence
With stress, Dit , Cit , A.T. Krishnan et al., IEDM 14.5.1, 2003
CGD
Important for analog circuits (Miller effect)
* B.C. Paul et al., IEEE Electron Dev. Lett. 26, 560 (2005)
 Circuit Degradation
# & ! RO
"# Change in
Accounts for $
Frequency Unity Gain
% '(
Model NBTI impact Degradation
$% % Bandwidth
on (Digital) (Analog)
VT
Shifted Channel charge -3.2% -1.0%
Model
Degraded Channel charge
$
I + V only
%+ +)Mobility
* -4.5% -1.3%
%Including
# Channel charge
GD
$
+ Mobility
) * +) -4.9%
+,-. -4.4%
+,-
,
$Degradation GD
$

VT shifted model captures only ~60% (20%) of

the degradation for digital (analog) circuits
A.T. Krishnan IRPS 2004
 Circuit Degradation
Degradation in digital circuits
FPGA performance
Ring oscillator fmax
SRAM static noise margin
Microprocessor
Degradation in analog circuits
Current mirror
Operational amplifier
 DC Versus AC Stress
Stress creates interface traps
( Si 3 Si )
Dit generation
Initially determined by
Si-H dissociation rate
Later determined by
hydrogen diffusion from
interface
When stress is terminated
hydrogen diffuses back
Interface traps are passivated
M.A. Alam, IEDM, 2003
dc: Dit generation
ac: Dit generation, passivation

ac stress leads to reduced degradation!

 Damage Relaxation
When stress is terminated, degradation relaxes
For sufficiently long times, all damage is healed
Important to indicate the time between stress
termination and NBTI measurements
17
Threshold voltage Recovery 1 ms after
Drain current 15
stress termination

IDlin (%)
Transconductance
13
Interface traps
Mobility 11
T=125 oC
9
10-3 10-2 10-1 100 101 102 103
Recovery Time (s)

S. Rangan et al., IEDM, 2003

 Damage Relaxation
For sufficiently long recovery time, damage
disappears
Temperature dependent
Higher temperature, less recovery
Hydrogen diffuses

Fraction Remaining
further from SiO2/Si 0.8
interface and is not T=125oC
available during
recovery 0.4 T=-40o, 25oC
If hydrogen diffuses Stress and recovery
all the way to the temperatures equal
0
poly-Si gate, it may 10-3 10-2 10-1 100 101 102 103 104
disappear Recovery Time (s)
S. Rangan et al., IEDM, 2003
 DC Versus AC Stress

Lifetime Enhancement
1000
Dynamic stress lifetime Duty cycle: 25%
Transistors in circuit switch 100
50%
at different frequencies
Some transistors may not 10 75%
T=125oC
switch out of NBTI state tox=1.8 nm
Could increase mismatch 1
100 101 102 103 104 105 106
between paths switching at
different rates Frequency (Hz)

1015
D-Inv
1013 D-Unipolar
D-Bipolar

Lifetime (s)
1011

109
107 f=100 kHz

105 T=125oC
tox=1.8 nm @ VT=30 mV
103
-0.5 -1 -1.5 -2 -2.5
S.S. Tan et al. IRPS, 35 (2004)
Gate Voltage (V)
 Effect of Hydrogen
Hydrogen commonly used for interface trap
passivation (~400-450C, 20-30 min)
Hydrogen can exist as
Atomic hydrogen H0
Molecular hydrogen, H2
Positively charged hydrogen or proton, H+
Part of the hydroxyl group, OH
Hydronium, H3O+
Hydroxide ions, OH-
Hydrogen is believed to be the main
passivating species for Si dangling bonds and
plays a major role during NBTI stress, when
SiH bonds are depassivated interface traps
 Effect of Nitrogen
Nitrogen may improve or degrade NBTI
NBTI enhanced by nitrogen
Nitrogen lowers activation energy
Nitrogen profile affects impact
Lower N at interface is better
Plasma nitridation gives least NBTI
1011
SiO2 Low
1010 Nitrogen
Lifetime (s)

109
10 Years
108 High
Nitrogen
107
VG=-1.2 V, tox=2.2 nm
106
2 3 4
1000/T (K-1)
N. Kimizuka et al., IEEE VLSI Symp. 92 (2000)
 Effect of Nitrogen
10
tox=6 nm
Grow thermal oxide T=125oC
NO anneal or plasma

IDsat (%)
1 VG=-3.6 V NO Annealed

nitridation
0.1
Reduced gate leakage
current (same oxide Plasma Nitrided Oxide
0.01
thickness) 100 101 102 103 104
Similar reliability Stress Time (s)
Improved NBTI with 1 1022
tox=3 nm
plasma nitridation
Nitrogen (cm-3)
8 1021
NO Annealed
Improves both digital 6 1021
and mixed-signal
4 1021
performance
2 1021
Plasma Nitrided Oxide
0
0 0.5 1 1.5 2 2.5 3
B.Tavel et al., IEDM, 2003 Depth (nm)
Effect of Nitrogen

B.Tavel et al., IEDM, 2003

 Effect of Water
Water in the oxide enhances NBTI
Dit and Qox increases are observed in damp and wet
oxides; diffusion species is water
Wet H2-O2 grown oxide to exhibit worse NBTI than dry
O2 grown oxides
Water is often present on wafers from contact and via
formation
Water and moisture mostly travel along interfaces
Water-originated reaction has lower energy at the
Si/SiOxNy interface than at the Si/SiO2 interface
NBTI is enhanced by water incorporation in oxide
 Effect of Fluorine
Fluorine improves NBTI
Hardens SiO2/Si interface
Fluorine is believed to relieve strain at SiO2/Si
interface
1
Normalized VT

0.8
tox=3.5 nm
0.6

0.4 tox=6.8 nm

0.2

0
0 1 1014 2 10 14 3 1014 4 1014 5 1014

Fluorine Dose (cm-2)

T.B. Hook et al., IEEE Trans. Electron Dev. 48, 1346 (2001)
 Fluorine
Incorporation of fluorine atoms
into SiO2 improves QBD
SIMS and Fourier transform F F F Poly-Si
infrared spectroscopy strained F F Gate
F
layers are localized near the
SiO2/Si interface O SiO2
Fluorine releases the distortion of Si Si
the strained Si-O bonds O OF OF
H F
Fluorine diffuses into gate-oxide Si Si Si Si Si Si
React with the strained Si-O bonds Strained Strain Re Si Si
and release the distortion Si-O Bond Release Oxidation

Released oxygen atoms re-oxidize Si

the Si-SiO2 interface
Forms Si-F instead of Si-H bonds
Si-F bond stronger than Si-H bond
Y. Mitani et al. Improvement of Charge-to-Breakdown Distribution by Fluorine
Incorporation Into Thin Gate Oxides, IEEE Trans. Electron Dev. 50, 2221, Nov. 2003
 Effect of Deuterium
Hot carriers degrade devices through: interface state
generation, oxide charge trapping,
mobility/transconductance degradation
Post metallization anneal (~450C/30 min):
forming gas or hydrogen H2: 1st Level Metal
106 H2: 5th Level Metal
Si-H bonds form at SiO2/Si 105
D2: 1st Level Metal
D2: 5th Level Metal

interface
Line Fit

Lifetime (s)
Line Fit
104
Si-H bonds easy to form, but 103
Deuterium

also easy to break

102 Hydrogen
Si-D bonds are stronger 101
(D: deuterium is a stable isotope 100
5% I D,sat Degrad.
of hydrogen with natural 10-6 10-5 10-4
abundance of 0.0015%) Substrate Current (A/ m)
Hot carrier resistance W. F. Clark et al., IEEE Electron Dev. Lett. 20, 501 (1999)
enhanced by D2
 Effect of Deuterium
Deuterium improves NBTI
A heavy variant of 100
Dry Oxidation
hydrogen

VT (mV)
Stable isotope of H2 PMA

hydrogen containing a 10
D2 PMA
proton as well as a

-
neutron in its nucleus VG = -2.9 V
tox=3.8 nm, T=150oC
Due to its heavier mass, 1
101 102 103 104
Si-D bonds are more Stress Time (s)
resistant than Si-H bonds
to hot carrier stress as
well as NBTI
 Effect of Oxide Thickness
VT shift, VT, depends on oxide thickness
VT ~ tox for same interface trap density
Qit qNit
VT = = tox
Cox Kox o

3 3
After Before Stress After Before Stress
2 2

1 1

Norm
Norm

0 0
tox=1.5 nm tox=5 nm
-1 T=125oC -1 T=125oC
E=10 MV/cm -2 E=10 MV/cm
-2
W/L=5/1 m W/L=4/0.5 m
-3 -3
-0.5 -0.4 -0.3 -0.2 -0.1 0 -0.5 -0.4 -0.3 -0.2 -0.1 0

VT (V) VT (V)

M. Agostinelli et al., IRPS, 171 (2004)

 Effect of Boron
Boron degrades NBTI
Boron diffuses into the 106
tox=6.5 nm

Lifetime (Years)
gate oxide from the 105
T=100oC
Without B Penetration
104
boron-doped gate and
103
from the source/drain 102 With B Penetration
implants 101
Reduced Dit due to Si-F 100
bonds from the BF2 boron 0 0.2 0.4 0.6 0.8 1 1.2

implant m)
Gate Length (
Enhanced Qox due to Yamamoto et al. IEEE Trans.
Electron Dev. 46, 921 (1999)
increased oxide defects
due to boron in the oxide
 NBTI Minimization
Have initially low densities of electrically active defects at
the SiO2/Si interface and keep water out of the oxide
Silicon nitride encapsulation layer has been found effective
in keeping water away from the active CMOS devices,
improving NBTI performance
Minimize stress and hydrogen content
Keep damage at the SiO2/Si interface to a minimum during
processing
Plasma damage degrades NBTI in p-MOSFETs, but not
n-MOSFETs
Deuterium improves both hot carrier stress and NBTI
Important to ensure deuterium can get to the SiO2/Si
interface and passivate dangling bonds or replace the
hydrogen with deuterium in existing Si-H bonds
 NBTI Minimization
Nitrogen incorporation has given conflicting
results. Some authors claim an NBTI
improvement, while others observe degradation
The method and chemistry of oxide growth has
significant effects on NBTI
Wet oxides show worse NBTI degradation then
dry oxides
Fluorine leads to an improvement. F in the gate
oxides can significantly improve NBTI and 1/f
noise performance
Boron degrades NBTI
Oxide electric field important
 Summary
NBTI
Can be a significant contributor to p-MOSFET
degradation in submicron devices
Needs to be considered during optimization
between device reliability and circuit
performance
Sensitive to a variety of process parameters,
e.g., hydrogen, nitrogen, fluorine, boron, etc.
Can occur during burn in
Can occur during circuit operation at elevated
temperatures
What Is It?