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ADSL Line Driver Design Guide, Part 2
ADSL Line Driver Design Guide, Part 2
Part one of this article appeared in the power dissipation. In an actual and there happens to be a significant
Linear Technology X:1 (February 2000) DSL design this approach overesti- level of noise interference and/or low
and is also available on the mates the typical power dissipation line impedance conditions. Design-
Linear T echnology web site at with a DMT signal by 10% to 20% ing to handle the conservative
www.lineartech.com/ezone/dsl.html. because a data transmission is not estimate provides a margin of safety
It discusses the different DSL stan- always at the maximum output power for reliable operation.
dards, characteristics of the DSL level. The DSP intelligence built into
signals, the design of differential driv- the system automatically adjusts the The Input Variables
ers for DSL and the requirements for transmitted power level and frequency Before a design can begin, the follow-
amplifiers used in this application. spectrum for each connection made. ing information must be known:
With shorter phone-line loops, the which DSL standard is to be used,
Design Calculations, Volts, transmitted power is reduced; with Full Rate or G.Lite, whether upstream
Amps and Power Dissipation longer loops, not all of the channels (CPE) or downstream (CO). These
It is very important to consider the are used and the number of data bits same equations apply for any DSL
power requirements of the line driver per channel is reduced. The maxi- standard (HDSL and HDSL2 for
in DSL applications. Although a nomi- mum transmitted power is provided example) with some changes to the
nal power level of 100mWRMS or less when the connection loop length is in input parameters (see Table 1).
into a 100 load does not seem to be the range of 4000 feet to 10,000 feet
a lot of power, the driver must handle
large peak signals and therefore Table 1. Input variables
requires a larger than nominal power
supply voltage. This increases both Typical Values for
the power dissipation in the driver Symbol Parameter Description ADSL
package and the peak current capa- 20dBm
bility needed from the power supply. (Full Rate, CO)
This issue becomes most critical in 16.3dBm
central office designs, where many PLINE (dBm) Line Power RMS power to be put on the line (G.Lite, CO)
DSL ports are included on a single 13dBm
card powered from one supply. Addi- (Full Rate and
tionally, the heat generated by the G.Lite, CPE)
drivers must be handled properly to Peak-to-average ratio for the DMT
ensure reliable operation. PAR Crest Factor 5.3
signal
This section will provide the calcu- Line Characteristic impedance of the
lations necessary to determine the ZLINE 100
Impedance line
voltages, currents and power dissipa-
tion for an ADSL driver of either The turns ratio of the line coupling
n Turns Ratio 1:1 or higher
standard. It can be quite useful to transformer
place these equations in a spread- The power loss of the transformer
PLOSS (dBm) Insertion loss 0.2dBm to 2dBm
sheet to allow quick observation of being used
the effect of different design variables A function of the output saturation
on the overall system. Assuming that voltages (positive and negative
Headroom
a wide band, low distortion driver has VHR swing) of the driver used. Head- 2V to 5V
Voltage
been selected (the LT1795 and LT1886 room is twice the larger of the two
are excellent choices), the three most saturation voltages.
important system issues to consider Total quiescent (no input signal)
are the total supply voltage, the peak Quiescent
IQ supply current of the driver that is 10mA to 30mA
output current and the driver power Current
not diverted to the load.
dissipation required. Maximum peak-to-peak differential
For these calculations, the RMS eIN Input Voltage input voltage from the AFE (analog 1.5V to 4.5VP-P
voltages required are treated as DC front end)
levels for the purpose of estimating
) )
is therefore able to swing fully to voltage to prevent peak signal clip-
Z PRI + ( 2 R BT) either supply voltage rail, and an ideal ping. Using a supply voltage greater
e PRI(RMS) transformer, with zero insertion power than this minimum value will increase
Z PRI
loss. A practical implementation will the power dissipation in the driver
require a larger supply voltage, as amplifiers.
MINIMUM DRIVER PEAK OUTPUT CURRENT (mA)
40 800
V+
MINIMUM TOTAL SUPPLY VOLTAGE (V)
30 600
G.LITE VS 2
VOUT
25 UPSTREAM VS 500 RSAT+ 3 RL = 25 RSAT+ =
G.LITE IPEAK IOUT
20 400 + 4
VSAT+ VHR VS = 15V
15 300 AMPLIFIER VEE
VOUT
OUTPUT 4 RSAT =
10 200 STAGE + IOUT
VSAT 3 RL = 25
LOAD
5 100 2 VOUT
UPSTREAM IPEAK
0 0 RSAT 1 RL = 2k
1 1.5 2 2.5 3 3.5 4 VSAT
V
TURNS RATIO (n) 50 25 0 25 50 75 100 125
VEE
TEMPERATURE (C)
Figure 1. Minimum peak-to-peak driver
output voltage and peak output current Figure 2. Typical output stage model and common data sheet curves
required, ideal amplifier and transformer are used to determine amplifier headroom voltage
2500
voltage drop and the voltage across resistance of 2.2.
2000
the resistor is called the output satu- With these values modeling the
ration voltage. The values to use to output saturation characteristics of 1500
model this characteristic can be the LT1795, at any level of peak out- 1000
CPE (15V)
determined from a data sheet curve. put current the output stage will 500 CPE (12V)
G.LITE CO (12V)
CPE (12V)
Figure 2 shows the curve that appears saturate or clip when swinging 0
1 1.5 2 2.5 3 3.5 4
on the LT1795 data sheet. towards the negative supply before it TURNS RATIO (n)
This curve shows the positive and will clip on the positive swing, due to ASSUMPTIONS
negative amplifier saturation voltages the higher effective series resistance FULL RATE G.LITE CPE
vs junction temperature with two dif- voltage drop. Transmission errors can IQ 28mA 18mA 14mA
VHR 3V 2.5V 2V
ferent values of load resistance. DSL occur if either output swing excur- PLOSS 0.5dBm 0.5dBm 0.5dBm
line drivers typically run warm, so the sion clips, so when sizing the total
area of interest on the curve will be in supply voltage requirement for the Figure 4. Driver power dissipation vs
the range of junction temperature driver the total headroom voltage of turns ratio: a practical implementation
) )
= eAMPLIFIERS(RMS) [PAR IQ + IPRI(RMS) Insertion Loss, 2.3% 2.3% 2.3%
PLOSS(dBm)
(PAR 1)] + (VHR + VEXTRA) PLOSS in dBm PMIN 1.023
0.1dBm
1
(IQ + IPRI(RMS))
ISUPPLY
0V
Designing for very low quiescent cur- R1
1.4V
rent significantly reduces the power 2mA
dissipation, but obtaining the lowest
distortion performance requires
additional biasing current for the IBIAS IBIAS
ON
internal amplifier circuitry. Figure 5 3V
VLOGIC
illustrates the adjustability of the SHDNREF
OFF
operating current for the LT1795. An 0V
internal current source is pro-
TIME
grammed via a single external resistor. ISUPPLY(ON) = 115 ION
SHDNREF IADJ
RADJ
0.75"
BOTTOM LAYER COPPER
0.75"
13MIL VIAS THAT FILL DURING THE PLATING PROCESS
TOP BOTTOM
40
LT1795CFE
vides a continuous path for heat trans- As most of the heat is dissipated in
20-PIN TSSOP PACKAGE fer from the junction of the IC, out of the area immediately surrounding the
38 WITH EXPOSED LEAD FRAME
FOR DIRECT METALLIC the plastic encapsulation, to pins that driver amplifier package, there comes
CONTACT TO PCB FOIL are directly connected to PCB copper a point of diminishing returns where
36
planes. An exposed lead frame does more copper area does not provide
JA C/W
not plastic encapsulate the under- much additional benefit. This can be
34
side metal where the IC is attached. seen in the plot of thermal resistance
This provides a metal pad that can be in Figure 7 where, beyond a total PCB
32
connected directly to PCB copper for area of 1in2, further reduction in ther-
direct transfer of heat from the IC mal resistance is minimal. One word
30
0.5 0.7 0.9 1.4 1.8 2.3 mounting junction heat source to the of caution regarding PCB planes for
TOTAL PCB FOIL AREATOP AND BOTTOM SIDES (IN2) ambient air. An exposed lead frame heat spreading is that the fiberglass
allows for very small packages, such material (typically FR-4) is a fairly
Figure 7b. Improving Heat dissipation as that used for the LT1795CFE, a good thermal insulator. Any compo-
with increased copper foil area
20-pin TSSOP, to have thermal con- nent interconnect traces that cut
times the overall thermal resistance ductivity characteristics similar to through the plane of copper signifi-
from the junction of the driver to the much larger sized packages. Very cantly reduce the effectiveness of the
ambient air will determine the rise in small packages with good thermal lateral area. Interconnect traces
operating junction temperature above conductivity can result in very dense should be made on the inner layers of
the maximum ambient temperature. multiport ADSL systems for central multilayer boards to minimize the
Most power amplifiers have a built in office applications. distance between components. The
thermal protection mechanism that The best way to spread the heat complex interconnect of the logic cir-
will disable the output stage when the generated by the driver is to use as cuits used in DSL modems usually
junction temperature exceeds typi- many planes of copper as are avail- requires a multilayer PC board that
cally 160C. Should this temperature able and to stitch them together can be put to good use in the line
ever be reached, the amplifier will through small vias from the topside of driver area.
protect itself, but data transmission the board to the bottom, as shown in Another measure that can be taken
errors will abound and most likely Figure 7. These vias should be small is to provide some forced airflow cool-
result in a data transmission discon- enough in diameter (15 mils or less) ing. A linear flow of air across the
nect. Designing a heat-spreading that they are completely filled with driver package can significantly
system to limit the driver junction solder during the plating process. This reduce the effective thermal resis-
temperature to less than 125C at the provides a continuous thermal con- tance from junction to ambient (JA)
highest expected ambient tempera- ductivity path from the top of the of the heat-spreading system. A re-
ture will ensure continuous operation. board to the bottom for the most duction of 2C/W to 3C/W for each
Fortunately, the power dissipation exposure to the ambient environment. 100lfpm (linear feet per minute) can
levels are not so high that external There are no fixed rules for determin-
heat sinks are necessarily required, ing the lateral area of the copper DRIVER
VCC
so heat spreading can usually be planes on the PCB, other than bigger V+ PIN
+
managed through planes of PCB cop- is better, and 2oz copper is a thicker 10F 0.1F 0.1F
per foil. In addition, the packaging of and therefore better thermal conduc- +
10F
most power amplifiers uses thermal tor than 1oz copper. Figure 7 also
provides an indication of the improve- +
conduction enhancements, such as 10F 0.1F 0.1F
fused or exposed lead frames. Fused ment in the heat spreading thermal DRIVER
VEE
lead frames have several package pins resistance from junction to case with V PIN
connected directly to the metal pad various amounts of copper foil area Figure 8. Recommended power
where the IC is attached. This pro- on the top and bottom sides of a PCB. supply bypassing for any design
gain of the amplifier stage is adjusted Figure 9. Basic differential receiver (4-wire to 2-wire)
to take into account the signal boost
of the transformer used as well as the
signal loss through the back-termi- to directly pick the small received filter/AFE. Many designs still prefer
nation resistors. signals out of the noise floor after to sense the differential signal across
Common to all of the designs is a passing through the receive/echo fil- the termination resistors and provide
good power supply bypassing ter. Other designs may use a second gain to the received signal before pass-
approach. This is shown in Figure 8. transformer to process the differen- ing it through the filter to the AFE.
A large- and a small-valued bypass tial received signal directly to the This basic differential receiver circuit
capacitor at the points where the sup-
plies connect to the board provide 0.1F 12V
decoupling of noise and ripple over a eIN+
wide frequency range. Additional high RC1 3 8
267 +
frequency decoupling at the driver CC1
A1 1 A RBT1 12.4 C
1/2 LT1886
and receiver supply pins is recom- 47pF 2 0.1F
T1
mended. Another large-valued bypass 1:2
RIN1
capacitor connected directly between 12V 20k eLINE
100
PHONE LINE
the supply pins of the driver helps to
RF1 1k
reduce the 2nd harmonic component RG1
10k 187
of ripple on the supply lines. This C1 0.1F
component comes from the peak cur- 1F
DRIVER CHARACTERISTICS
eIN
rent demands from each supply, + 1F C2 eLINE
1F AV = =6
which occur twice for each input sig- 10k
RG2
eIN
187 POWER CONSUMPTION: 470mW
nal cycle due to the differential RF2 1k
POWER DISSIPATION: 425mW
amplifier topology (each amplifier PEAK DRIVER CURRENT: 159mA
Line Drivers
Part LT1795 LT1207 LT1886 LT1497 LT1206 LT1210
Single/Dual Dual Dual Dual Dual Single Single
Output Current 500mA 250mA 200mA 125mA 250mA 1.1A
Supply Voltage 10V to 30V 10V to 30V 5V to 13V 5V to 30V 10V to 30V 10V to 30V
Gain Bandwidth
50MHz 60MHz 75MHz 50MHz 60MHz 35MHz
Product
Slew Rate 900V/s 900V/s 200V/s 900V/s 900V/s 900V/s
IQ/Amplifier 1mA to 30mA 1mA to 30mA 7mA 10mA 1mA to 30mA 1mA to 50mA
+
VSAT 1.2V 1.2V 0.75V 1.2V 1.2V 1.2V
VSAT 1.2V 1.2V 0.9V 1.15V 1.2V 1.25V
RSAT +
1.2 3.2 3.1 14 3.2 0.9
RSAT 2 5.3 2.3 10 5.3 1.7
Dual-Amplifier Receivers
Part LT1355 LT1358 LT1361 LT1364 LT1813 LT1253
Supply Voltage 5V to 30V 5V to 30V 5V to 30V 5V to 30V 5V to 12V 10V to 24V
Gain Bandwidth 12MHz 25MHz 50MHz 70MHz 100MHz 90MHz
Slew Rate 400V/s 600V/s 800V/s 1000V/s 750V/s 250V/s
Noise Voltage 10nV/Hz 8nV/Hz 9nV/Hz 9nV/Hz 8nV/Hz 3nV/Hz
IQ/Amplifier 1.25mA 2.5mA 5mA 7.5mA 3mA 6mA
Conclusion
Using these abbreviations: account the turns ratio and trans- Following the design procedures
For proper impedance matching: P = former insertion loss. described in this article should make
1 K. The use of a high performance the design and implementation easy
To obtain a desired voltage gain amplifier such as the LT1795 does and accurate. At the very least, it will
from the AFE output to the line, AV, not result in any degradation of dis- ensure that power and heat issues
the term G is set to: tortion performance when modifying receive proper consideration.
the closed-loop gain by positive feed- Linear Technology offers a variety
A e
G = V PRI (1 + K P) P (17) back. Significant power savings can of high speed, low distortion power
eLINE be obtained but the design may not be amplifiers and low noise dual ampli-
where ePRI and eLINE are the voltages suitable for all applications as previ- fiers that can be used to implement
at the transformer primary and on ously mentioned. the driver/receiver functions of the
the line, determined by taking into DSL modem (see Table 3).
Authors can be contacted For more information on parts featured in this issue, see
at (408) 432-1900 http://www.linear-tech.com/go/ltmag