Professional Documents
Culture Documents
LowPowerMethodsRTL PDF
LowPowerMethodsRTL PDF
Jin-Fu Li
Advanced Reliable Systems
y ((ARES)) Lab.
Department of Electrical Engineering
National Central University
Jhongli, Taiwan
Outline
Introduction
Low-Power Gate-Level Design
Low-Power Architecture-Level Design
Algorithmic-Level Power Reduction
RTL Techniques
T h i for
f Optimizing
O i i i Power
P
D
Dynamic
i power di
dissipation
i ti d during
i switching
it hi
Cinput
interconnect
Cdrain Cinput
Vout
VA nMOS C drain Cint erconnect Cinput
VB network
1 T /2 dVout T dVout
Pavg [ Vout (Cload )dt (VDD Vout )(Cload )dt ]
T 0 dt T /2 dt
VA VA
Vinternal VB
VB Cinternal Vinternal
Vout
VA VB Cload Vout
i
P i (1 P i ) C i
A 0.2 0.0384
0.0196
B 0.2 0.0099
C 0.5
D 0
0.5
5
A
B
C A 0.2
D 0.0384
B 0.2
C 0.5 0.0099
D 0
0.5
5 0.1875
National Central University EE4012VLSI Design 9
Gate--Level Design Phase Assignment
Gate
A
A
B
B
C
C
a b c d a b c d
d a
Switchin
Switching activityy
c b
ng activity
b c
a d
d a
c
b b
a c
d
A
A
B
B D
C
E D
C
E
C Chain structure
D
B Tree structure
C
D
REG REG
Combinational Logic
R1 R2
REG REG
Combinational Logic
R1 R2
Precomputation
Logic
g
A<n-1>
A<n 1> REG 1-bit Comparator
B<n-1> R1 (MSB)
REG
A<n-2:0>
R2
(n-1)-bit REG
Enable
Comparator R4
Precomputation logic F
REG
B<n-2:0>
R3
D Q D Q D Q D Q
Fail DFT rule
clk checking
T
Add control pin
D Q D Q D Q D Q to solve DFT
violation
problem
clk
f1
clk
+
select
l t
f2
D D Q
CK
D D Q D Q D Q D Q
multiiplexer
Output
D Q D Q D Q D Q
CK(f/2)
Flip-flops are operated at full voltage and half the clock frequency.
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 19
Power Consumption of Shift Register
1 33 0
33.0 1535
ed power
2 16.5 887
4 8 25
8.25 738 05
0.5
ormalize
0.25
No
C. Piguet, Circuit and Logic Level
Design pages 103-133
Design, 103 133 in WW. Nebel 00
0.0
and J. Mermet (ed.), Low Power 1 2 4
Design in Deep Submicron Degree of parallelism, n
Electronics Springer,
Electronics, Springer 1997
1997.
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 20
Architecture--Level Design Parallelism
Architecture
16 16
A R A R
32 16 32
16x16 16x16
fref fref/2
multiplier multiplier
16 R
B R
M 32
U
fref fref/2 X
32 Half Half 32
(A ,B) REG REG
multiplier multiplier
fref
V ref
Ppipeline 1 .2 C ref ( ) f ref 0 .36 Pref
2
1 .83
National Central University EE4012VLSI Design 22
Architecture--Level Design Retiming
Architecture
Retiming is a transformation technique used to change the
locations of delay elements in a circuit without affecting the
input/output characteristics of the circuit
circuit.
w2(n)
(2) (2)
REG C1 C2 REG C3
((6ns)) ((2ns)) (4ns)
fref
REG C1 REG C2
C3
(6ns) (2ns)
(4ns)
fref
C2
C1
C1_FREEZE
C2_FREEZE
C2
C1
C1_FREEZE
FREEZE
C2_FREEZE
A segmented
g bus structure
Switched capacitance during each bus access is
significantly reduced
Overall routing area may be increased
Cbus
Cbus1
Interface
Bus
Cbus1
a
Present
Next state
state A
b
a b A B
B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
A = ab + ab CK
B = ab + ab CLR
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 31
Binary Counter: Gray Encoding
Present a
Next state
state
A
a b A B
0 0 0 1 B
b
0 1 1 1
1 0 0 0
1 1 1 0
A = ab + ab CK
B = ab + ab CLR
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 32
Three--Bit Counters
Three
Binary Gray-code
State gg
No. of toggles State No. of toggles
gg
000 - 000 -
001 1 001 1
010 2 011 1
011 1 010 1
100 3 110 1
101 1 111 1
110 2 101 1
111 1 100 1
000 3 000 1
Av. Transitions/clock = 1.75 Av. Transitions/clock = 1
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 33
N-Bit Counter: Toggles in Counting Cycle
Xi/Zk
Si
Sk Xk/Zk
C oc ca
Clock can be stopped
Sj Xj/Zk when (Xk, Sk) combination
occurs.
PI
Combinational
logic PO
Flip-fflops
Clock
activation Latch
logic L. Benini and G
L G. De Micheli
Micheli,
Dynamic Power Management,
CK Boston: Springer, 1998.
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 37
Bus Encoding for Reduced Power
Example: Four bit bus
0000 1110 has three transitions.
If bits of second pattern are inverted
inverted, then 0000
0001 will have only one transition.
Bit-inversion encoding for N-bit bus:
N
ding
ons
Number of bit transitio
n encod
after iinversion
N/2
0
0 N/2 N
N b off bi
Number bit transitions
ii
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 38
Bus--Inversion Encoding Logic
Bus
ed data
nt data
Sen
Receive
R
Bus register
Polarity
M. Stan and W. Burleson, Bus-Invert
decision
Polarity bit Coding for Low Power I/O, IEEE
logic
Trans. VLSI Systems, vol. 3, no. 1, pp.
49-58, March 1995.
Source: Prof. V. D. Agrawal
National Central University EE4012VLSI Design 39
RTL--Level Design
RTL Signal Gating
Initial Reordered
stable M
Mux
A<B Mux
glitchy
glitchy
lit h
Mux A<B Mux
stable
128x32
din
32
addr dout
write
noe
8 M 32
q addr[7:0]
[ ]
pre addr
pre_addr d addr[7:1]
dd [7 1] U dout
X
clk noe
write
addr dout
din 32
addr0 128x32
Reads
64K bytes
Data
ARM
Addr
Core
R/W
Addr
28K 4K 32K Range
64K
Decoder
ARM
R/W
Addr
CS
Data
R/W
Addr
R/W
Addr
CS
Data
CS
Data
Core