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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Power and Delay Analysis of CMOS Multipliers

using Vedic Algorithm

Raj Kumari I and Rajesh Mehra2

iDepartment of Electronics & Communication Engineering, NITTTR Chandigarh
2Department of Electronics & Communication Engineering, NITTTR Chandigarh
E-mail: ikumari09raj@gmail.com.2rajeshmehra@yahoo.com

Abstract-This paper presents an effective Vedic 3. Final Addition

algorithm called as Urdhva-Tiryyagbhyam Sutra
These basic multiplication steps are shown in Fig.
implementation and design for multipliers using 45nm
below:
technology. Multiplier is one of the most important parts of
MULTIPLICAND MULTIPLIER
almost all digital system hardware, so a high speed, reduced
delay, reduced area and low power consumption multiplier
design will results in effective digital system designs. Thus
this paper present an effective design and implementation of
a multiplier with high speed, reduced delays, less area and Partial Product Generator
low power consumption using our ancient methodology of ****
Vedic mathematics that is Urdhva-Tiryagbhyam Sutra. This
implementation is done in 45nm technology using chip ****
designing tool Cadence Virtuoso at backend. Implemented
****
Multiplier consumes very low power because of its carry skip
addition methodology, reduced hardware and reduced ****
delays. A 2 Bit multiplier consumes a very low power
5.5489xlO -\I watt and delay of 1.924xlO -12 sec and 4 Bit
multiplier consumes power of 0.0002854 watt and delay of
7 *******
2.0873xlO- sec.
Keywords: Vedic Algorithm, Multiplier, Verilog, VLSI, ****
Adder
Partial Product Arrav Reduction
I. INTRODUCTION

Most important arithmetic operation performed

almost in all digital signal processors and systems is
multiplication operation [1]. Multiplication is involved in
all digital signal and data processing. Thus performance of
a system completely depends upon the performance of its
multiplier unit. The speed, power consumption and area of
a multiplier define performance of a system. This paper
presents layout and simulation of a multiplication
algorithm which is suitable for low power, low delay and
high performance applications [2]. Multipliers are utilized
to implement any operation because these are fast, reliable
and efficient components. These are of number of types
and depending upon the application a specific type of
multiplier is chosen. In a simple way multiplication is a
process of adding an integer called as multiplicand to itself
a number of times specified by another integer called as
multiplier. Also multiplication is considered as a process
of add and shift operations. But in case of digital systems
multiplication has three basic concepts:
l. Generation of partial product arrays.
2. Reduction of partial product array
********
Final Addition
Fig. I: Basic Multiplication Flow
To generate partial products at first stage n shifted
copies of multiplicand are generated and then added
according to the bits of multiplier. AND gate logic can be
used at this stage. At second stage of partial product
reduction mainly addition is done to perform reduction and
this stage results into the optimization of design in terms of
area, power and delays. It depends upon the type of
technique used to perform reduction. Generally a
compressor circuit is used for reduction. And final addition
is done by using an efficient carry propagate adder [3].
II. VEDIC MULTIPLICATION ALGORITHM
From ancient Indian scriptures referred to as Vedas an
ancient form of mathematics has been reconstructed which
is known as Vedic Mathematics [4]. It has different
branches of mathematics like algebra, arithmetic,
trigonometry based on 16 sutras of Vedic mathematics.

978-1-4673-8587-9/16/$31.00 2016 IEEE [1]

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Most generalized sutra which is also used for the

implementation of this Vedic algorithm is Urdhva Xo Xl Xo Xo
Tiryagbhyam which reduces the number of bits results in

X
reduced area and delays [5].Vedic Multiplier thus has
become very popular for faster computations and analysis.
This sutra is based on the principle of Vertical and
YI Yo YI Yo YI Yo
Crosswise and only utilizes AND gate, Half Adder and
Full Adders for multiplication process which saves large
amount of processing time [6]. Traditionally this method
is used to perform fast multiplication of two decimal Fig. 3: Two Bit Multiplication using Vedic Methodology
numbers by using vertical and cross as can be seen in
Here two 2 bit binary numbers X = XIXO and Y =

Fig. 2:
YIYO are multiplied using vertical and cross technique. xo,
Yo are multiplied and generate LSB bit of result [8]. Then
cross multiplication of XOYI and XIYO is performed and
product terms are added also carry of previous stage is
added to this and thus generate next bit of result. At final
stage XIYI are multiplied vertically and added with carry
of previous stage and then addition is taken as MSB bits
of the result. A simple architecture to perform this 2 bit
multiplication can be given as shown in Fig. 4:

Xo yo

I HALF ADDER I

I HALF ADDER I

C2 82 81 80

Fig. 4: Two Bit Multiplication Architecture

Fig. 2: Decimal Multiplication using Vedic Methodology
In this process of multiplication as shown in the Fig.
1. 2 also the digits along the vertical line are multiplied
with each other and summed up and also previous carry is
added to the total. This generates a sum bit and a carry bit
which is added to the next stage and not propagated
further. In this whole process only LSB bit is considered
as result bit and rest are considered as carry for next stage
[7]. At last the carry generated is taken as the MSB of
result.
A. 2 Bit Vedic Multiplier Algorithm
Using similar process of multiplication 2 bit binary
multiplication can be performed in few numbers of steps.
This can be given as in Fig. 3:
As seen in Fig. 4 only an AND gate logic and half
adder circuitry is sufficient to perform the multiplication
operation so it is clear that this methodology is very much
effective in optimizing the area, delays and thus power
consumption of VLSI design which is of most concern in
designing [9].
B. 4 Bit Vedic Multiplier Algorithm
A 4 bit Vedic multiplier algorithm is similar to 2 bit
multiplier and implementation is also done with the help
of 2 bit Vedic multipliers and adders. To implement this
partial product terms are generated using 2 bit Vedic
multiplier and then partial reduction and addition step is
done with the help of simple adder circuit. A simple 4 bit
ripple carry adder circuit can be used. Adder is the basic

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

building block of multiplier and multiplier is building Gate as shown in Fig. 6. In the design of Multiplier this
block for Arithmetic Logical Unit, Microprocessors and AND gate plays important role to generate partial products
Digital Signal Processors [10]. terms for next stage of multiplier.

v. V.M V.

__--I.y

S7 S6 S5 S4 S

Fig. 6: AND Gate Schematic

Fig. 5: Four Bit Vedic Multiplication Architecture (2) XOR Gate Schematic: XOR gate simulation is
Thus an efficient design for multiplier is implemented implemented with only 4 numbers of transistors. It uses
but leakage power has become a serious concern in nm two PMOSs and two NMOSs which perform the operation
CMOS technology [11]. of pull up and pull down n finally implements XOR gate
logic in which output is generated only when two different
III. IMPLEMENTATION OF MULTIPLIER SCHEMATIC input logics are applied. In this implemented schematic a
very less delay is achieved and also power consumption is
For implementation of 2*2 Vedic Multiplier in this
very less as shown in Table 1.
paper 45nm technology is used and work is done on
transistor level. The whole implementation is done step by
step starting from transistor level to module level. VDD
1. Create a library and attach it to the technology on
which design is to implement here is 45nm. PM PM1
2. Then by using transistors from 45nm library "g45p1svt' " g 45p 1sv!'
. w:12n w:12n
implement AND gate logic which is used in the
circuit for Partial Product generation. 1:45n 1:45n
m;l m;l
3 . Symbol for AND logic i s created and imported
into the newly created library.
4. Then in Partial product Array reduction XOR A
y
gate is implemented for further implementation
of Half Adder. Symbol of it is created and
NM NMI
imported into the library. l'g45n1sv.i"
w;120n
5. XOR and AND are further called into the
implementation of Half Adder and used for final 1;45n
m:.l
addition.
6. In this way a 2*2 Vedic Multiplier is
implemented and power, delay and transistor
count is calculated. vss
(1) AND Gate Schematic: AND gate is simulated
using a very compact design in which only two NMOS
Fig. 7: XOR Gate Schematic
transistors are used to implement operation of AND logic

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

(3 ) Half Adder Schematic: Half Adder is simulated
with the help of AND Gate and XOR Gates which are
simulated at first and after that their symbols are imported
from the library and directly Half Adder get is
implemented with very less no. of transistors only six thus
delay experienced is also very small and very low power
consumption.
(5) Full Adder Schematics: A Full Adder is simulated
with the help of already simulated Half Adder and OR
gate Symbols as shown in Fig. 10. This Adder is
implemented with mmlmum delays and power
consumption. After the designing of a Full Adder 4-bit full
adder is implemented using 4 units of the full adder. The
implementation of this 4-Bit full adder is shown in Fig. 11
which is very much simplified and has very less delays.
aN

.-----------B OR Y f--tt-__ SUM

.----1I--1 VDD
B' YSS
A.

'" ...-=---------

o Fig. 10: Full Adder Schematic

z

iI--__ CARRY

Fig. 8: Half Adder Schematic

(4) 2 Bit Multiplier Schematic Simulation: A two bit

multiplier is implemented with the help of AND Gates and
Half Adders. Simple principle of partial product
generation and addition of those partial products is
followed and thus two bit Vedic multiplier is designed
with minimum numbers of transistors 20 and minimum
delay and power consumption. Schematic is shown in
Fig. 9.
Fig. I I: 4 Bit Full Adder Schematic
(6) 4 Bit Multiplier Schematic Simulation: A 4Bit
multiplier is implemented using four 2 Bit multipliers and
simple 4 Bit adders. This design is also based on the
principle of partial Product generation and reduction.
Schematic is shown in Fig. 12.

---+

Fig. 9: 2*2 Multiplier Schematic Fig. 12: 4 Bit Multiplier Schematic

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

IV. SIMULATION AND RESULTS Also total delay is calculated for the circuit and power
consumption which is very less as shown in Table 1.
Simulation results are shown in Fig. 13 in which two
Table 1 thus shows that a very low power consumption is
bit numbers 11 and 11 are multiplied using Vedic
achieved using this Vedic implementation and also delays
multiplier design. And as a result we get four bit output SO
are minimized which increases the speed of this design.
= 1, S2 0, S3 = 0, C2 1. Waveforms for all these
= =

multiplier, multiplicand and result bits are shown. Also TABLE I: SIMULATION RESULTS

total delay is calculated for the circuit and power Sr. Schematics Transistor Delay Power
No. Count
consumption which is very less as shown in Table 1. 11
I. AND 2 162.2x10- I.2945x IO-LJ
S
I. I
Jil W
GI
,
' ..11
I
lI 2. XOR 4 49.96xI0-12
s
7.8927xI0 -12
w
I IL
I. I I 52.28xI0 -IL S 7.9798x I0 -
;Jil l I
1 3. Half Adder 6
11 W

I. I

lI
4. 2 Bit 20 192.4xI0-ILs 5.5489x 10 -
G.I
Multiplier w
'-.11
Iil 5. Full Adder 14 27.46x10-IL s 5.7819xIO -
I. I
'-
II 6. 4 Bit Full 56 2.768xI0-12 s
w
2.867x10 -9
I
I
I" , II

; ool l I
1 Adder W
11 7. 4 Bit 248 2.087x10- s 0.0002854
I I ll r
--L-----/r Multiplier W

ool l l
'111.1 These results can also be shown wIth the help of a bar
I I chart where direct visualization of simulated results is
r

10
,111.1
g r
lOO.1
!
'111. 1 ' possible as shown in Fig. 15.

,100.1
I '''''iiii"' 'i""iiilij
&1 .I hi 100 250
'111,51 200

-
150
Fig. 13: 2*2 Multiplier Simulated Output 100 v:: - - - - - - - - 1'-
50 -- -.- -.- .- .- - - 7
o -

A simulation result of 4*4 bit multiplier is shown for Transistor Count

Ij
Cl i> i> i> i>
"0 "0 "0
input 1111 and 1111. At output we are having 8 bit output
0
X "0
-< "0 "0 Delay
that is 10101001. On verifying this output using Vedic ,... .. :; -< -<
t;i :2 :; :; Power
:c: - ... ...
I
multiplier we have observed that a very less power is
consumed and delay is minimized to a great extent. This Cii Cii
N ..;- I"'"
output of 4*4 bit multiplier is shown in Fig. 14.
IN ,

I] I il II I 2 3 4 5 6 7

I. I il.!! If
:i!
I I G.! I I Fig. 15: Graph of Transistors Count
I. I il If
I. il! II
V. CONCLUSION
I
.0
:i! '
I. I G.! I Efficient Vedic Multiplier is implemented in VLSI
, Ii Cadence Virtuoso tool, 45nm technology by using an
I. I G.! II
ii II
ancient Vedic algorithm. Effective low power and high
I I performance adder circuit is used for the implementation
:i!
G.! I of multiplier such that more efficient Vedic multiplier
I
I I ) l'
till
design can be executed. This multiplier is much faster than
that of other conventional multipliers and also consumes
,I i
I
II low power because of its carry skip addition methodology,
,I i'
I
II reduced hardware and reduced delays. Delay of Multiplier
I
.Il' circuit is minimized to.2087I;1S. Total power calculated for
1M
!II I i i iiii i II i I i iii iii i iiiiii iiiiii iii i
II I I this circuit is. 2854mw which is very less. Thus further
!I I hi implementation of higher order multipliers can be done
'I
with very low power consumption and also minimum
Fig. 14: Simulated Output of 4*4 Multiplier delays.

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

REFERENCES

[I] B. S. Premananda, S. S. Pai, B. Shashank, S. S. Bhat, "Design and

Implementation of 8-bit Vedic Multiplier", International Journal of
Advanced Research in Electrical, Electronics and Instrumentation
Engineering, Vol. 02,no. 12,pp. 5877-5882,December 2013.
__,.W.>;dI "'. Raj Kumari: Er. Raj Kumari is
[2] N. H. E. Weste and D. M. Harris, "CMOS VLSI Design", Pearson
Publications,4th Edition,pp. 476- 490,1998. currently pursuing M.E from National Institute of
[3] P. Balasubramanian and J. John, "Low Power Digital Design Technical Teachers Training and Research, Chandigarh
[4] Using Modified GDI", IEEE Transactions on Circuits and Systems, India. She has completed her B. Tech from H.P.
Vol. 41,no.1I,pp.730-739,August 2009. University, Shimla, India. She is having 3 years of
[5] A. Kant and S. Sharma, "Applications of Vedic Multiplier Designs teaching experience. She has one paper in her credit. Her
- A Review", IEEE International Conference on Reliability,
areas of interest include Advanced Digital Signal
Infocom technologies and Optimization, pp. 58-62, September
2015. VLSI Design and Embedded System.
I"!'III'
[6] R. Saligram, T. R. Rakshith, "Optimized Reversible Vedic
Multiplier for High Speed Low Power Operations", IEEE
Conference on Information and Communication Technologies, pp.
809-814,April 2013.
[7] N. Pokhriyal and N. R. Prakash, "Area Efficient Low Power Vedic
Multiplier Design using GDI Technique", International Journal of r. Rajesh Mehra: Dr. Mehra is
Engineering Trends and Technology, Vol. 15, no.4, pp.196-199, currently associated with Electronics and Communication
September 2014.
Engineering Department of National Institute of Technica]
[8] M. Sowmiya, N. Kumar, S. Valarmathy and S. Karthick, "Design
Teachers' Training & Research, Chandigarh, India since
of Efficient Vedic Multiplier by Analysis of Adders", International
Journal of Engineering Technology and Advanced Engineering, 1996. He has received his Doctor of Philosophy in
Vol. 3,no.l,pp. 396-403,January 2013. Engineering and Technology from Panjab University,
[9] P. Balasubramanian and J. John, "Reliable Low Power Multiplier Chandigarh, India in 2015. Dr. Mehra received his Master
Design", IEEE Transactions on VLSI Systems, Vol. 23, no.l, of Engineering from Panjab University, Chandigarh, India
pp.78-87, January 2015.
in 2008 and Bachelor of Technology from NIT, Jalandhar,
[10] R. Kumari,M. Priya and S. Chand,"A Survey on Low Power VLSI
Designs", International Journal of Electrical and Electronics
India in 1994. Dr. Mehra has 20 years of academic and
Engineering, Vol. 2,no.I,pp.56-6I,May 20I5. industry experience. He has more than 3 25 papers to his
[II] A. Sharma, R. Singh and R. Mehra, "Low Power TG Full Adder credit which are published in refereed International
Design Using CMOS nano Technology", IEEE Conference on Journals and Conferences. Dr. Mehra has guided 75 ME
Parallel Distributed and Grid Computing, pp. 2I0-2I3, December thesis. He is also guiding 02 independent PhD scholars.
2012.
He has also authored one book on PLC & SCADA. He has
[12] P. Saini and R. Mehra, "Leakage Power Reduction in CMOS VLSI
Circuits", International Journal of Computer Applications, Vol. 55,
developed 06 video films in the area of VLSI Design. His
no.8,pp. 42-48,October 20I2. research areas are Advanced Digital Signal Processing,
[13] R. Verma and R. Mehra, "CMOS Based Design Simulation of VLSI Design, FPGA System Design, Embedded System
AdderlSubtractor Using Different Foundries", International Journal Design, and Wireless & Mobile Communication. Dr.
of Science and Engineering, Vol. 2, no.l, pp.28-34, November
Mehra is member of IEEE and ISTE.
2013.

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