Srivats Iyer

Cell: (817) 915-1966

Email: i.srivats@gmail.com LinkedIn: www.linkedin.com/in/getsrivatsiyer/

Summary
I am an Electrical Engineer and my specialties are RTOS, Embedded Systems and Firmware
development, Microcontrollers, Microprocessor design and architecture. I enjoy taking on new
challenges and working with highly motivated people who think out of the box.
Skills
Languages: C, C++, Assembly, Python, Verilog.
Microprocessor (8/16/32 bits): Intel X86, ARM7, ARM Cortex A8.
Microcontroller (8/16/32 bits): Intel MCS-51, ARM Cortex M4F.
FPGA: Altera Cyclone III.
SoC: TI AM335x.
Modules: UART, SPI, I2C, I2S, CAN, Ethernet, Bluetooth.
Peripherals: GPIO, PWM, Timers, ADC, DAC.
Protocols: RS-232, RS-485, USB, TCP/IP, UDP, HTTP.
Embedded OS: RTOS, Linux (Experience working on BeagleBone Black).
Software: Eclipse IDE, TI Code Composer Studio, Eagle, Cadence OrCAD, Altium, Visual
Studio, Microsoft Office, Microsoft Visio etc.
Version Control: GIT.
Tools: Oscilloscope, Logic Analyzer, Protocol Analyzer.
Employment
Cognitech, Inc. (Pasadena, California) -----------------(January 2017 to August 2017)
Worked as a hardware engineer during my internship at Cognitech, Inc. I was the
principal engineer involved in a redesign of Cognitech's proprietary Video Capture
Card. This card is designed for decoding analog video, digital video and digital audio.
Replaced the video decoder chip with the Analog Devices 7842 series of video
decoder chips.
Responsible for component selection, creation of the schematic circuit design and
high-speed layout design.
Ran signal integrity analysis on the new design using Cadence PCB design
software. Since the individual ICs had different impedance requirements, I designed
an impedance controlled, layer stackup for the board.
Managed the prototyping process by communicating with PCB manufacturers and
assembly vendors overseas.
Wrote firmware to control and monitor video output from the capture card. During
this process, I worked on ThreadX RTOS, Altera FPGA, USB, I2C and I2S protocols.
Designed the video controller using Verilog to manage and forward the video
output from FPGA.
Wrote firmware for the USB Controller chip to output the video for viewing. The
USB firmware included designing of state machines, ping-pong scheme for the
DMA buffers, writing USB descriptors and creating USB endpoints. Coding was
done using embedded C in an RTOS environment.

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 Srivats Iyer
Cell: (817) 915-1966
Email: i.srivats@gmail.com LinkedIn: www.linkedin.com/in/getsrivatsiyer/

Education
MS in Electrical Engineering | Graduating December 2017
The University of Texas at Arlington
Embedded Microcontrollers, Microprocessor Systems, Advanced Embedded
Microcontrollers, Advanced Microprocessor Systems, Computer Architecture II, Computer
Networks. (Current GPA 3.6).

Relevant Academic Projects

Design of Pre-emptive and Cooperative Real Time Operating System for ARM Cortex
M4F microcontrollers.
Design of a cooperative and preemptive RTOS right from scratch defining yield, wait,
sleep and post functions.
Supports semaphores, yielding, system timer, SVC call handler, PendSV call handler,
along with priority scheduler, priority inheritance and shell commands like PS, IPCS,
KILL, PIDOF etc.
Unmanned Vehicle navigation (TM4C123GH6PM microcontroller - ARM Cortex M4F
family).
To design and control the navigation of an unmanned vehicle that moves along a
magnetic field path.
The Hall Effect Sensors along the vehicle, help in sensing the magnetic field and
determine the path.
RTOS was implemented on the TM4C123GH6PM microcontroller and the motion
control application kept the vehicle centered along the lane.
Bluetooth was used to achieve remote control.
Design of a 32-bit RISC Microprocessor.
Design of a 32-bit RISC microprocessor with 4 stage pipeline (Instruction Fetch /
Decode, Register Read /Address generator, Fetch Operand / Execution, Write Back).
Developed complete instruction set (32-bit).
Stall-based structural hazard resolution.
Stall and data forwarding-based resolution for data hazards.
Asynchronous memory interface logic.
Cache Controller Architecture for 32-Bit Processor.
To determine the best architecture for a cache controller that interfaces to a 32-bit
microprocessor with a 32-bit data bus. While the microprocessor is general purpose
in design and performs several functions, it is desired to speed up certain signal
processing functions, such as a fast Fourier transform (FFT) routine.
This architecture is verified on a Radix-2 FFT routine.
This architecture is verified for different burst lengths and set associativity.
The code is written on a Visual Studio Platform using C++.

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