1 _________________ 3 __________________

___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Documentation of a digital system
provides the necessary information for
___________________ Basic Rules of Block Diagram ___________________
___________________ ___________________
A block diagram must show the most
building, testing, operating , and important system elements and how
maintaining the system. they work together.

Generally, documentation include:

A Specification that describes what the
___________________ Each block diagram should not be more
than 1 page.
Large systems may require additional
___________________
___________________ ___________________

circuit is supposed to do.
block diagrams of individual
A block diagram showing the inputs, subsystems. A subsystem is another
outputs, the main building blocks or

___________________ ___________________
block that has a whole system in it.
modules of the system and how they
are connected. Important control signals and buses in
A schematic diagram showing all the the block diagram should have names.

___________________ ___________________

components, their types, and all Flow of control and data should be
interconnections. clearly indicated.
A timing diagram showing the logic

___________________ ___________________
The schematic diagram inside the block
signals as a function of time. need not to be shown.
A structured logic device description
showing the operation of the structure
A Circuit description explaining of the
operation of the logic circuit. ___________________ ___________________
Combinational Logic Design Practices * Property of STI
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___________________ Combinational Logic Design Practices * Property of STI
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___________________

2 _________________ 4 __________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Block Diagram ___________________ Schematic Diagram ___________________
___________________ ___________________
shows all inputs and outputs, the Things to follow in doing schematic
building blocks, their function names, diagrams:
and the data flow paths or the logic

signals.
Related logic signals are combined
together and drawn with a double or
___________________ Details of component inputs, outputs,
and interconnections
Reference designators
___________________

heavy line, known as a bus
Example: Min/Max Circuit ___________________ Pin numbers
Gate symbols
Signal names and active levels
___________________
___________________ Bubble-to-Bubble Logic Design
Layouts
Logic diagram: An informal drawing
___________________
___________________ ___________________

without this level of details.

___________________
___________________
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___________________
___________________
___________________
Combinational Logic Design Practices * Property of STI
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___________________
 5 _________________
___________________
Advanced Logic Circuit
Documentation
Standards
___________________
Example of Schematic Diagram ___________________
___________________
___________________
___________________
___________________
___________________
___________________
___________________
Combinational Logic Design Practices * Property of STI
Page 5 of 63
___________________
6 _________________
___________________
Advanced Logic Circuit
Documentation
Standards
___________________
Signal Names ___________________
___________________
Signal name is a descriptive
alphanumeric label for each
input/output signal.
In real system, well-chosen names
convey information to readers.
A signal name indicates
___________________
___________________
An action that is controlled like
ENABLE, REQUEST, GO, PAUSE
___________________
A condition that it detects such as
READY_L, ERROR,
Data that it carries, such as
___________________
INBUS[31..0], ADDR[150]
___________________
___________________
___________________
Combinational Logic Design Practices * Property of STI
Page 6 of 63
7 __________________
___________________
Advanced Logic Circuit
Documentation
Standards
___________________
Active Levels ___________________
___________________
Each signal name should have an
active-level associated with it, normally
it is a + or symbol that denotes high
or low.
A signal is active-high if it performs the
named action or denotes the named
___________________
condition when its HIGH or 1. A signal
is active-low if it performs the named
action or denotes the named condition
___________________
when its LOW or 0.
Different naming conventions for active
___________________
___________________
levels are available.
___________________
___________________
Combinational Logic Design Practices * Property of STI
Page 7 of 63
___________________
8 __________________
___________________
Advanced Logic Circuit
Documentation
Standards
___________________
Active Levels Naming Conventions ___________________
___________________
___________________
___________________
___________________
___________________
Active low signal has a suffix of _L as
___________________
part of the variable name.
Example:
___________________
ERROR is an active high which
means there is an error when the
signal is HIGH ( logic 1).
READY_L is an active low which
___________________
means the data is ready when the
signal is LOW ( logic 0).
Combinational Logic Design Practices * Property of STI
Page 8 of 63
 9 _________________ 11 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Example of Naming Conventions ___________________ Active Levels for Pins ___________________
___________________ ___________________
The outline of a logic symbol, means that the
given logic function is occurring inside that
outline.

___________________ ___________________
In logic gates and logic structures the inversion
bubble indicates the active level of the signal
Examples:

___________________ ___________________
- 2-to- 4 Decoder

- EN_L is active low

___________________ - A and B are active high

- Y0_L, Y1_L, Y2_L,Y3_L are active low

___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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10 ________________ 12 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Signal Name, Logic Expression, Logic
Equation
___________________ Bubble-to-Bubble Logic Design Rules ___________________
A signal name uses any variable name
in alphanumeric label.
___________________ ___________________
A logic expression combines signal
names using switching algebra
operators such as AND,OR, and NOT
___________________ ___________________
A logic equation is an assignment of a
logic expression to a signal name. It ___________________ ___________________
___________________ ___________________
describe one signals function in terms
of other signals.
For example: READY_L, READY are
signal names. READY is a logic
expression. ___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________
 13 ________________ 15 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Drawing Layouts ___________________ Hierarchical Schematic Structure ___________________
___________________ ___________________
Inputs to the left/top, outputs to the
right/bottom.
Signals flow from left to right (or top to

bottom).
Signal paths should be connected. ___________________ ___________________
___________________ ___________________
Broken signal paths should be flagged
to indicate the source or destination
and direction.
Crossing lines/Connected lines (T-type
connection)
Multiple pages schematics:
___________________ ___________________
___________________ ___________________

Flat Structure
Hierarchical Structure

___________________ ___________________
___________________ ___________________
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___________________

14 ________________ 16 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Documentation
Standards Standards
___________________ ___________________
Drawing Layout: Flat Schematic
Structure
___________________ Rules to avoid common errors in signal
convention:
___________________
___________________ Use exactly the same name for same
signal. Use different names for different
___________________
___________________
signals. (especially cross pages)
Use appropriate active levels for signal
names
___________________
___________________ Use T convention for connected lines.
___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________
 17 ________________ 19 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Documentation Programmable Logic

Standards Devices
___________________ ___________________
Buses ___________________ Why PLDs? ___________________
___________________ ___________________
Buses should be named : DATA[0:7], Fact:
CONTROL
It is most economical to produce an IC
A bus name may use brackets and a colon to in large volumes

___________________ ___________________
denote a range
But:
Buses are drawn with thicker lines than
ordinary signals. Many situations require only small
volumes of ICs

___________________ ___________________
Individual signals are put into or pulled out
of the bus by connecting an ordinary signal Many situations require changes to be
line to the bus and writing the signal name. done in the field, e.g. Firmware of a
product under development

___________________ ___________________
(A special connection dot is often used.)
A signal extracted from a bus should be
named A programmable logic device can be:

___________________ ___________________
Inter-page signal/Bus Flags: Produced in large volumes
Uni-direction
Programmed to implement many
Bi-direction
different low-volume designs

___________________ ___________________
Example of buses:

___________________ ___________________
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___________________

18 ________________ 20 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Programmable Logic Programmable Logic

Devices Devices
___________________ ___________________
An integrated circuit with internal logic
gates and/or connections that can be
___________________ PLD Hardware Programming
Technologies
___________________
changed by a programming process
Examples of PLD:
___________________ In the Factory - Cannot be
erased/reprogrammed by user
___________________


PROM
Programmable Logic Array (PLA) ___________________ Mask programming (changing the VLSI
mask) during manufacturing
Programmable only once
___________________
___________________ ___________________
Programmable Array Logic (PAL) device

Complex Programmable Logic Device Fuse

(CPLD) Anti-fuse

___________________ ___________________
Field-Programmable Gate Array (FPGA) Reprogrammable (Erased &
A PLDs function is not fixed Programmed many times)
Can be programmed to perform Volatile - Programming lost if chip power

___________________ ___________________

lost
different functions
Single-bit storage element
Non-Volatile - Programming survives

___________________ power loss

UV Erasable ___________________
___________________ ___________________
Electrically Erasable
Flash (as in Flash Memory)

Combinational Logic Design Practices * Property of STI

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___________________
 21 ________________ 23 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Programmable Logic
Decoder
Devices
___________________ ___________________
Used symbol in PLD ___________________ Truth Table of 2-to-4 Decoder ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
Most PLD technologies have gates with
very high fan-in
___________________ ___________________
Fuse map: graphic representation of
the selected connections ___________________ ___________________
___________________ ___________________
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___________________

22 ________________ 24 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Decoder Decoder
___________________ ___________________
Accepts a value and decodes it ___________________ 2-to-4 Decoder ___________________
___________________ ___________________
Output corresponds to value of n
inputs

A decoder is consists of:

Inputs (n)
___________________ ___________________
Outputs (2n , numbered from 0 2n -
1) ___________________ ___________________
___________________ ___________________
Selectors / Enable (active high or active
low)

___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________
 25 ________________ 27 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Decoder Decoder
___________________ ___________________
Truth Table of 3-to-8 Decoder ___________________ Combinational Circuit Design with
Decoders
___________________
A A A D D D D D D D D
2 1 0 0 1 2 3 4 5 6 7
___________________ A decoder provides an output of 2n
minterms (sum of products) with n
___________________
0 0 0 1 ___________________
input variables
Any Boolean function can be expressed
as a sum of minterms at the output
___________________
0 0 1 1
___________________ A decoder and external OR gates can be
used to implement any combinational ___________________
0 1 0 1
___________________ ___________________
function.

0 1 1 1
1 0 0 1 ___________________ ___________________
1 0 1
1 1 0
1
1
___________________ ___________________
1 1 1 1 ___________________ ___________________
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___________________

26 ________________ 28 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Decoder Encoders
___________________ ___________________
3-to-8 Decoder ___________________ Perform the inverse operation of a
decoder
___________________
___________________ 2n (or less) input lines and n output
lines
___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________
 29 ________________ 31 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Encoders Encoders
___________________ ___________________
___________________ Can be implemented with 3 OR gates ___________________
___________________ ___________________
A0 = D1 + D3 + D5 + D7;
A1 = D2 + D3 + D6 + D7;
A2 = D4 + D5 + D6 + D7;

___________________ If more than 2 inputs are active we need

to use ___________________
___________________ ___________________
priority encoder (priority for inputs)

___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________

30 ________________ 32 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Encoders Encoders
___________________ ___________________
Encoders with OR Gates ___________________ Priority Encoder ___________________
___________________ ___________________
Accepts multiple input values instead
of just having one input that is high,
and encodes them

___________________ Works when more than one input is

active
Consists of:
___________________
___________________ ___________________

Inputs (2n)
Outputs

___________________ ___________________
when more than one input is
active, sets output to correspond to
highest input

___________________ ___________________
Selectors / Enable can still be active
high or active low

___________________ ___________________
___________________ ___________________
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___________________
 33 ________________ 35 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Encoders Multiplexer
___________________ ___________________
Encoder vs. Decoders ___________________ Multiplexer: 2-to-1 ___________________
___________________ S = 0 selects I0
___________________
Decoder Encoder ___________________ ___________________
___________________ ___________________
___________________ ___________________
Binary decoders/encoders
___________________ ___________________
n-to-2^n
Input code : Binary
2^n-to-n encoder
Input code : 1-out-of-
___________________ ___________________
___________________ ___________________

Code 2^n.
Output code :1-out-of- Output code : Binary
2^n. Code

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___________________

34 ________________ 36 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Multiplexer Multiplexer
___________________ ___________________
A multiplexer switches (or routes) data
from 2N inputs to one output, where N
___________________ Multiplexer: 2-to-1 with Enable ___________________
is the number of select (or control)
inputs.
___________________ ___________________
A multiplexer (mux) is a digital switch
___________________ ___________________
with multiple inputs and one output. It
is also considered as a circuit that is
many to one. It selects what input
___________________ ___________________
signal goes sequentially to the output
link.
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________ Combinational Logic Design Practices * Property of STI
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___________________

Multiplexer
Multiplexer: 4-to-1
Two select signals
Y = (I0.s1's0') + (I1.s1's0) + (I2.s1s0') + (I3.s1s0)
Combinational Logic Design Practices
Multiplexer
Multiplexer 4-to-1
Select signal for
second level of decoders
Select signal for
first level of decoders
Combinational Logic Design Practices
37 ________________ 39 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit
Multiplexer
___________________ ___________________
___________________ MUX: Designing Logic Circuits ___________________
___________________ ___________________
Each row in a Truth Table of a
multiplexer corresponds to a minterm
with N-inputs
___________________ Each minterm can be mapped to a
multiplexer input, so there will also be
N minterns
___________________
___________________ For each row in the Truth Table, where
the output of the function is one (F = 1), ___________________
___________________ ___________________
Set the corresponding input of the
multiplexer to 1
___________________ ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
* Property of STI Combinational Logic Design Practices * Property of STI
Page 37 of 63 Page 39 of 63
38 ________________ 40 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit
Multiplexer
___________________ ___________________
___________________ MUX: Designing Logic Circuits
Efficiently
___________________
___________________ ___________________
Each row in a Truth Table corresponds
s to a minterm
___________________ ___________________
1
N-input Truth Table
s0
A product term of N-1 variables can be
mapped to each of the multiplexer
w
0 0
___________________ inputs
(N-1)-input Multiplexer
___________________
w
1 1
___________________ For the rows in the Truth Table,
Group N-1 highest order inputs into
pairs
___________________
___________________ ___________________
0
f Define the output of each pair using the
1 Nth input
w
2
3
0
1
___________________ ___________________
___________________ ___________________
___________________ ___________________
2-to-1 Muxes
* Property of STI Combinational Logic Design Practices * Property of STI
Page 38 of 63 Page 40 of 63
 41 ________________ 43 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Multiplexer Demultiplexer
___________________ ___________________
MUX: Designing a Logic Circuit ___________________ It is a circuit that switches (r routes
data from one input to 2N outputs,
___________________
___________________ where N is the number of select
inputs.
___________________
___________________ It performs the opposite function of a
___________________
___________________ multiplexer.
___________________
___________________ It is also considered as a circuit that
has many one to many outputs. ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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___________________

42 ________________ 44 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Multiplexer Demultiplexer
___________________ ___________________
MUX: Designing a Logic Circuit ___________________ Demultiplexer: 1-to-4 ___________________
___________________ 0
1
O0
O1
___________________
___________________ I
2 O2 ___________________
___________________ ___________________
3 O3

s1
___________________ s0 ___________________
___________________ S1 S0 O O O O
0 1 2 3
O0 = S1'.S0'.I ___________________
___________________ 0 0 I 0 0 0
0 1 0 I 0 0
O1 = S1.S0'.I
___________________
___________________ ___________________
O2 = S1'.S0.I

1 0 0 0 I 0 O3 = S1.S0.I

Combinational Logic Design Practices * Property of STI

Page 42 of 63
___________________ 1 1 0 0 0 I
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___________________
 45 ________________ 47 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Exclusive OR and Exclusive OR and

Exclusive NOR Gates Exclusive NOR Gates
___________________ ___________________
XOR :
___________________ XOR Application: Parity Circuit ___________________
___________________ ___________________
Odd Parity Circuit : The output is 1 if
odd number of inputs are 1
XNOR :
X Even Parity Circuit : The output is 1 if
Truth Table :
F
___________________
even number of inputs are 1
Example : 4-bit Parity Circuit ___________________
___________________ ___________________
XOR
X Y XOR XNOR
0 0 0 1
0 1 1 0 Y
1
1
0
1
1
0
0
1 ___________________ ___________________
XOR X
F ___________________ ___________________
( X Y )' = X Y + X 'Y '
X Y = X 'Y + X Y ' ___________________ ___________________
Y
___________________ Input: 1101 Odd Parity output : 0 ___________________
___________________ ___________________
Even Parity output : 1

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Page 45 of 63 Page 47 of 63

46 ________________ 48 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Exclusive OR and
Equality Comparator
Exclusive NOR Gates
___________________ ___________________
XOR and XNOR Symbols ___________________ XNOR
___________________
___________________ ___________________
Equivalent Symbols of XOR Gate X Y Z
0 0 1

___________________ ___________________
X 0 1 0
1 0 0
Z 1 1 1

___________________ ___________________
Y

Equivalent Symbols of XNOR Gate

___________________ Z = !(X $ Y) ___________________
___________________ ___________________
___________________ ___________________
___________________ ___________________
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 49 ________________ 51 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Equality Comparator Equality Comparator

___________________ ___________________
4-Bit Equality Comparator ___________________ 4-Bit Magnitude Comparator ___________________
A0 C0
___________________ A_LT_B
___________________
___________________ ___________________
A[3..0]
B0 Magnitude
Detector
A1 C1 A_EQ_B

A2
B1 A_EQ_B
___________________ B[3..0]
A_GT_B
___________________
A3
B2 C2 ___________________ ___________________
B3 C3 ___________________ ___________________
FIELD A = [A0..3];
___________________ ___________________
___________________ ___________________
FIELD B = [B0..3];
FIELD C = [C0..3];

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50 ________________ 52 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Equality Comparator Equality Comparator

___________________ ___________________
4-Bit Equality Detector ___________________ TTL Comparators ___________________
___________________ ___________________
1 20
P>Q Vcc
1 16 2 19

___________________ ___________________
B3 Vcc P0 P=Q
A[3..0] Equality 2 15 3 18
Detector A<Bin A3 Q0 Q7

___________________ ___________________
A_EQ_B 3
A=Bin B2 14 4
P1 P7
17
B[3..0]
4 13 5 16

___________________ ___________________
A>Bin A2 Q1 Q6
5 12 6 15
A>Bout A1 P2 P6

___________________ ___________________
6 11 7 14
A=Bout B1 Q2 Q5
7 10 8 13

___________________ ___________________
A<Bout A0 P3 P5
8 9 9 12
GND B0 Q3 Q4

___________________ ___________________
10 11
74LS85 GND P4

Combinational Logic Design Practices * Property of STI

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___________________ Combinational Logic Design Practices
74LS682
* Property of STI
Page 52 of 63
___________________
 53 ________________ 55 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Equality Comparator Equality Comparator

___________________ ___________________
Cascading Two Comparators ___________________ 4-Bit Magnitude Comparator ___________________
A3 A2A1 A0 A7 A6A5 A4 ___________________ x3 y3 x2 y2 x1 y1 x 0 y0 ___________________
10
12
13
P0
P1
10
12
13
P0
P1
___________________ G4 G2
___________________
___________________ ___________________
P2 P2
G3 G1 G0
gt
15
2
P3 P<Q
7 15
2
P3 P<Q
7
A<B eq 1-bit comp 1-bit comp 1-bit comp 1-bit comp
Gin=0
< < lt Lin=0
___________________ ___________________
3 6 3 6
+5V 4
= P=Q
4
= P=Q A=B L4 L3 L2 L1 L0
> >
9 5 9 5
A>B
___________________ ___________________
Q0 P>Q Q0 P>Q
11 11
Q1 Q1
14 14 X Y
Q2 Q2 1101 0110
1 1 gt = 1
Q3 Q3
___________________ 1110
1011
0101
1011
1011
0111
eq = 1
lt = 1
___________________
B3 B2B1 B0 B7 B6B5 B4 ___________________ 1010 1011
___________________
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54 ________________ 56 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Adders, Subtractors,
Equality Comparator
and ALU
___________________ ___________________
1-Bit Magnitude Comparator ___________________ Half Adder: Adds two 1-bit operand ___________________
___________________ ___________________
Truth Table
x y

Gout
___________________ ___________________
___________________ ___________________
1-bit Gin
Eout comparator

___________________ ___________________
Lout Lin

The variable Eout is 1

___________________ HS = X Y ___________________
if A = B and Gin = 0 and Lin = 0.
The variable Gout is 1 ___________________ CO = X Y ___________________
___________________ ___________________
if A > B or if A = B and Gin = 1.
The variable Lout is 1
if A < B or if A = B and Lin = 1.

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___________________
 57 ________________ 59 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Adders, Subtractors, Adders, Subtractors,

and ALU and ALU
___________________ ___________________
Full Adders: Provide for carries
between bit positions
___________________ Ripple Adder ___________________
Basic building block is full adder
1-bit-wide adder, produces sum and
___________________ ___________________

carry outputs
Truth table: ___________________ ___________________
X
0
Y
0
Cin
0
S
0
Cout
0
___________________ ___________________
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
___________________ ___________________
1
1
1
0
0
1
0
1
0
1
0
0
0
1
1
___________________ Speed limited by carry chain
___________________
___________________ ___________________

1 1 1 1 1 Faster adders eliminate or limit carry
chain

___________________ ___________________
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58 ________________ 60 _________________
___________________ ___________________
Advanced Logic Circuit Advanced Logic Circuit

Adders, Subtractors, Adders, Subtractors,

and ALU
___________________
Full Adder Circuit ___________________ Subtraction
___________________
and ALU
___________________
___________________
___________________
Subtraction is the same as addition of
the twos complement.
The twos complement is the bit-by-bit

___________________
___________________
___________________
___________________
___________________
___________________
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___________________ Combinational Logic Design Practices
complement plus 1.
Therefore, X Y = X + Y + 1 ,
subtraction can be performed by using
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adder circuits.
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* Property of STI
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Advanced Logic Circuit Advanced Logic Circuit

Adders, Subtractors, Adders, Subtractors,

and ALU and ALU
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Full Subtractor = Full Adder, almost ___________________ Arithmetic Logic Units (ALU) ___________________
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An arithmetic-logic unit, or ALU,
performs many different arithmetic and
logic operations. The ALU is the heart

___________________ of a processor
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X,Y are n-bit unsigned binary numbers
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Addition : S=X+Y
Subtraction : D = X - Y = X + (-Y) =
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= X+ (Twos Complement of Y)
= X+ (Ones Complement of Y) + 1
= X+ Y+ 1

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Combinational Logic Design Practices * Property of STI
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___________________ Combinational Logic Design Practices * Property of STI
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62 ________________
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Advanced Logic Circuit

Adders, Subtractors,
and ALU
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Using Adder as a Subtractor ___________________
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Ripple Adder can be used as a
Subtractor by inverting Y and setting
the initial carry ( CIN ) to 1

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Combinational Logic Design Practices * Property of STI
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