LAKSHMI NARASIMHAN RAMAKRISHNAN

3238, Bishop Street, Apt#2, Cincinnati, Ohio -45220 Email: ramakrln@mail.uc.edu Phone: 312-513-4176

OBJECTIVE Graduate student seeking opportunities in Physical Design, Design Automation, RTL Design,
Low power Circuit Design, ASIC Design, Embedded System, Verification, Validation & Testing

EDUCATION
University of Cincinnati - Masters - Computer Engineering (VLSI Track) 3.92/4.0 Sep2008 – Sep2010.
Sastra University - Bachelor of Technology in ECE. 87% June2004 – May2008

RESEARCH - ( Advisor: Dr.Ranga Vemuri )

“Design of a generic Register-file architecture resistant to DPA attacks” - Side Channel Attack resistance via dynamic power
masking in read and write cycle of the register file. – Presented in the Graduate Poster Symposium – University Of Cincinnati.

“Design Techniques for cryptographic circuits resistant to Leakage power based DPA” – Analysis and reduction of leakage
power due to stack effect in WDDL implementations. – Presented in the ECE-CS Poster Symposium – University of Cincinnati.

SOFTWARE PLATFORMS, TOOLS & IDE

Synopsys Tools: Design Compiler, Power Compiler, DFT Max, Tetramax ATPG, Hspice, Nanosim, Prime Time, VCS, Synplify.
Cadence Tools: Virtuoso Schematic Composer, Encounter RTL Compiler, Encounter Timing System.
Other Tools: Magic Layout Editor, Irsim, Cosmoscope, AvanWaves, Modelsim, Simics, Pspice, Orcad, Labview, Matlab.
FPGA & Microcontrollers: Altera Quartus II, Xilinx ISE Design suite, Actel Libero IDE, Keil IDE, TI MSP430 & 8051 Series.
Programming: C, C++, VHDL, Verilog, ABEL, X86 Assembly Language, 8051 & PIC uc, basics of JAVA,VC++ & VB.
Scripting: Perl, Unix Shell Scripting, VB Scripting, basics of Tcl.
Operating Systems: Solaris, Unix, Mac OS X, Linux (Ubuntu & Fedora), Windows Series.

PROJECTS

 Designed and taped out a chip (Fall – 2008) at University of Cincinnati to detect the presence of a route between
two nodes in a specified direction (NE), from a given set of 100 nodes. Freq: 700 Mhz, Technology used in this
project : AMI C5 0.5 nwell process, 38 bidirectional pins, 1.5mm x1.5mm area and feature size 0.6u.

 Developed a Design Automation tool for balanced circuit bi-partitioning, implementing KL algorithm and tested
the tool with benchmarks of various sizes (Used GNU C++).

 Developed Design Automation tool for placement and routing of cells for a set of given benchmarks. Placement
tool was based on Force Directed Placement algorithm and routing tool was based on Channel Routing algorithm.

 Tested my Router Chip designed with testing tools (Tetramax ATPG generator, HP Logic Analyzer) and also
generated alternate design (DFT Strategies) which enhances testing for my chip.

 Implemented a basic high level working model of Hybrid NoC in C++ and Simics and evaluated the performance
against Regular NoC. For evaluation 4 routers, 16 processor NoC and 9 routers, 36 processor NoC were considered.

 Designed a low power Dual Port SRAM memory array using Magic. Implemented various power reduction
techniques at transistor, gate and logic level - analyzed its performance and power consumption using Hspice.

 Designed a `Pipelined General Purpose Microprocessor’ on FPGA. Specifications: 45 instructions, 6 addressing

modes, Pipelined (5 levels), logics to deal with data hazards, 1Kb of memory. Tested against Benchmark programs
 Designed a low power Full Adder using Magic and analyzed its performance and power using Hspice. Measured
the various source of power consumption for various input combinations, input slope and transistor sizes.

 Designed an Embedded Restaurant Automation System using Texas instrument’s MSP430 microcontroller.

 Designed an Embedded System for Intelligent Cruise Control -a technology that aids cars to detect the speed
limits in different zones and control the speed of the cars within the specified norms of each zone. A body electronic
sensor in the car detects accident and intimates it to the nearest hospital through a text message using GSM.

 Boundary Scan Design: Inserted an internal scan chain into a given design performing GCD implementation.
Used Synopsys DC compiler for boundary scan chain insertion & generated test pattern using Tetramax ATPG.

 Designed an intelligent autonomous Robot for the international robotics contest - Robocon 2006

 Designed a quick Maze Solving Robot that won the 2nd prize in the national level contest held at PSG Tech

 In-plant training-Worked in R&D Dept of “TVS ELECTRONICS” towards issues in Speed 40 Pass Book printer

RELEVANT COURSEWORK

GRADUATE: Physical VLSI Design, Design Automation, VLSI Testing and Validation, VLSI System Design, Low power
VLSI, Computer Architecture, Embedded systems, Design and Analysis of Algorithm, Automata and Formal Languages,
Digital Design Environments, Advanced Low power VLSI and Testing.

UNDERGRADUATE: Electronics 1 & 2, Digital Design, Linear Integrated Circuits, DSP , PC Hardware, VLSI-1, Operating
Systems, Computer Organization, RTOS, Computer networks, Numerical Methods, Microprocessors, Microcontrollers.

HONORS AND AWARDS

 Best technical performer of the batch 2004-08 -- Sastra University.
 Texas instrument Best MSP430 Microcontroller Project Award - 2007 organized and conducted by Texas Instruments.
 Best project award in the MAGNUM OPUS – a National Level Technical Symposium.
 Dean’s List - Sastra University - for the academic year 2004 – 2005.
 University Graduate Scholarship (2008-2010) University Of Cincinnati.
 Second Place in Graduate Poster Symposium –ECECS Dept -- University Of Cincinnati.
 First in national level Hardware Design Contest organized by Sastra University.
 Second in the National Level Project Presentation contest Dhruva. (PSG Tech).
 A certificate of merit for innovative autonomous robot design in the international robotics competition Robocon 2006.
 University Topper in Analog Modulation Systems, Microwave Engineering and Transmission Lines.
 Ranked 4th in National Level Electronic Circuit Design and Debugging contest at NIT– T.

RESPONSIBILITIES HELD
 President of ECE-GSA at University of Cincinnati.
 President and coordinator of the Sastra University Robotics Club.
 Research Assistant for the Automation Research Group in Tifac Core @ Sastra University.

REFERENCE
Dr.Ranga Vemuri (Advisor), Professor, ECE Dept, University of Cincinnati Email: ranga.vemuri@uc.edu