character 7-bit ASCII my_arrayright any_type 0

integer signed 32 bit at least my_arrayascending boolean false

natural integer >= 0 my_arraylength integer 10
positive integer > 0 my_arrayrange integer 9 downto 0
real Floating point, min : +1e38 to -1e38 my_arrayreverse_range
string Array of characters integer 0 to 9
VHDL Quick Reference Card time hr, min, sec, ms, us, ns, ps, fs fourvalleftof(0)
fourvalleftof(1)
fourval
fourval
error
0
6.2 User Defined Data Types fourvalpos(Z) integer 2
type range is range 0 to 100000 fourvalpred(1) fourval 0
1. Introduction units fourvalrightof(1) fourval Z
VHDL is a case insensitive and strongly typed language. meter; -- base unit fourvalsucc(Z) fourval X
Comments start with two adjacent hyphens (--) and end at kilometer = 1000 meter; fourvalval(3) fourval X
end of line. end units distance; sigactive boolean
type number is integer; True if activity on sig
type voltage is range 0 to 5; sigdelayed(T) sigtype
2. Compilation Units Copy of sig delayed by T
Library Usage Declarations -- ref. 11 type current is range 1000 downto 0;
type d_bus is array ( range <> ) of bit; sigdriving_value sigtype
Entity Declarations -- ref. 3 Value of driver on sig
Architecture Declarations -- ref. 4 type instruction is record
opcode : bit; sigevent boolean
Package Declarations -- ref. 10 True if event on sig
Configuration Declarations -- ref. 14 operand : bit;
end record; siglast_active time
type int_file is file of integer; Time since last activity
3. Entity Declaration type pointer_to_integer is access integer; siglast_event time
entity n_input_nand is subtype positive_number is integer range 0 to 100000 Time since last event
generic ( n : integer := 2); type fourval is ( X, L, H, Z ); siglast_value sigtype
port ( data : in bit_vector( 1 to n ); subtype resolve_n is resolve twoval; Value before last event
result : out bit ); sigquiet(T) boolean
end n_input_nand Activity ( now T ) to now
-- port directions : in | out | inout | buffer | linkage 7. Declarations sigstable(T) boolean
constant bus_width : integer := 32
Event ( now T ) to now
variable read_flag : bit := 0;
4. Architecture Declaration sigtransactio bit
-- only in processes
architecture behave of n_input_nand is Toggles on activity on sig
-- and subprograms
-- declarations -- ref. 7 signal clock bit;
begin file f3 : int_file open write_mode is test.out; 9. Statements
-- concurrent statements -- ref. 9 alias enable : bit is addr(31); 9.1 Concurrent Statements
end behave attribute delay : time; state_mach : process ( state ) -- label is optional
component n_input_nand -- variable declarations -- ref. 7
5. Operators generic ( n : integer := 2 ); begin
logical operators : and, or, xor, nand, nor, xnor, not port ( data : in bit_vector ( 1 to n ); -- sequential statements -- ref. 9
relational operators : =, /=, <, <=, >, >= result : out bit ); end process;
shift left/right logical operators : sll, srl end component n_input_nand; U1_n_input_nand : n_input_nand
shift left/right arithmetic operators : sla, sra function square ( i : integer ) return integer; generic map ( n => 2 )
rotate lefet/right logical operators : rol, ror for store : use configuration latch; port map ( data => my_data;
other operators : +, -, &, *, **, /, mod, abs, rem result => my_res );
eg. & : concatenation, 1 & 10 = 110 8. Attributes top_block : block
** : exponentiation, 2 ** 3 = 8 -- type my_array is array ( 9 downto 0 ) of any_type; -- declaration -- ref. 7
rem : remainder, 7 rem 2 = 1 -- variable an_array : my_array; begin
mod : division modulo, 5 mod 3 = 2 -- type fourval is ( 0, 1, Z, X ); -- concurrent statements -- ref. 9
-- signal sig : sigtype; end block;
6. Data Types -- constant T : time := 10 ns; label1 : for i in 1 to 3 generate
Attribute Result type Result label2 : nand2( a(i), b(i), c(i) );
6.1 Predefined Data Types end generate
bit 0 and 1 my_arrayhigh any_type 9
my_arrayleft any_type 9 label3 : if ( i < 4 ) generate
bit_vector Array of bit label4 : nor2( a(i), b(i), c(i) );
boolean true and false my_arraylow any_type 0
 end generate; end if; type std_logic_vector is array
return return_val; ( natural range <> ) of std_logic;
9.2 Sequential Statements end bool_2_2level; function to_bit ( s : std_ulogic; xmap : bit := 0 ) return bit;
null; -- does nothing function to_bitvector
wait on sig1, sig2 until ( sig = 1 ) for 30 ns; procedure clock_buffer ( s : std_logic_vector; xmap : bit := 0 )
wait until ( clockevent and clock = 1 ); ( signal local_clk : inout bit; return bitvector;
read_flag := 0; -- read_flag is a variable signal clk_pin : in bit; function to_stdlogicvector ( b : bit_vector )
if ( x < y ) then max := y; constant clock_skew : in time ) is return std_logic_vector;
elsif ( x > y ) then max := x; -- optional begin function rising_edge ( signal s : std_ulogic ) return boolean;
else max := x; -- optional -- example of side effects in a procedure function falling_edge ( signal s : std_ulogic ) return boolean;
end if; global_clk <= local_clk after clk_skew; function is_x ( s : std_logic_vector ) return boolean;
case a is local_clk <= clk_pin;
when 1 | 0 => d <= 1; end clock_buffer; 16.2 STD.TEXTIO Package
when Z => d <= 0; type line access string;
when others => d <= X; -- optional 13. Predefined Subprograms type text is file of string;
end case; enable <= 1 when ( now < 2 ns ) else 0; type side is ( right, left );
while ( x < y ) loop variable ptoi : pointer_to_integer; subtype width is natural;
next when ( x > 5 ); -- usage of next ptoi := new integer; -- usage of new file input : text open read_mode is std_input;
x := x + 1; deallocate ( ptoi ); file output : text open write_mode is std_output;
end loop; variable status : file_open_status; procedure readline ( file f : text; I : out line );
for i in ( 0 to 100 ) loop file my_file : int_file; procedure writeline ( file f : text; I : in line );
x := x + i; file_open( status, my_file, in.dat, read_mode ); procedure read ( I : inout line;
exit when ( x = 0 ); -- usage of exit end_file ( my_file ); -- returns true/false value : out bit;
end loop; variable int_var : integer; good : out boolean );
read ( my_file, int_var ); procedure write ( I : inout line;
9.3 Concurrent and Sequential Statements file_close ( my_file ); value : in bit;
enable <= select after 1 ns; justified : in side := right;
assert ( a = b ) 14. Configuration Declarations field : in width := 0 );
report a is not equal to b -- The type of value can be bit_vector | boolena |
configuration input_8 of n_nand is
severity note; -- character | integer | real | string | time.
for customizable
-- severity levels : note | warning | error | failure -- There is no standard package for textio operations on
for a1 : nand_2
-- std_logic. Tools vendors may provide their own.
use entity work..nand_2 ( n_nand_arch );
10. Package Declarations end for;
package two_level is end for; 16.3 IEEE.NUMERIC_STD Package
-- type, signal, functions declarations -- ref. 7 end input_8; type unsigned is array ( natural range <> ) of std_logic;
end two_level; type signed is array ( natural range <> ) of std_logic;
function shift_left ( arg : unsigned; count : natural )
package body two_level is 15. Non-synthesizable Constructs return unsigned;
-- subprogram definitions -- ref. 7 Most tools will not synthesize :
end two_level; -- Other functions: shift_right(), rotate_left(),
access, after, alias, assert, bus, disconnect, file, guarded,
rotate_right()
inertial, impure, label, linkage, new, on, open, postponed, function rsize ( arg : signed; new_size : natural )
11. Library Usage Declarations pure, reject, report, severity, shared, transport, units, return signed;
-- using the two_level package. with.
library work;
VHDL Quick Reference Card is intended for quick reference.
use work.two_level.all; -- all objects used 16. Standard Packages Please use VHDL LRM of 1993 for details.
use work.two.level.vcc; -- only the vcc object used Samplings of a subset of standard packages the language
provides.
12. Subprograms
function bool_2_2level ( boolean : in_bool ) 16.1 IEEE.STD_LOGIC_1164 Package
return two_level is type std_ulogic is ( U, X, 0, 1, W, L, H );
variable return_val : two_level; -- MLV9
begin type std_ulogic_vector is array
if ( in_bool = true ) then ( natural range <> ) of std_ulogic;
return_val := high; function resolved ( s : std_ulogic_vector ) return std_ulogic;
else return_val := low; subtype std_logic is resolved std_ulogic;