68 Digital Engineering with VHDL

IEEE Library Declarations

Essential VHDL 7
Every VHDL file should begin with library declarations. Generally these will
be the IEEE libraries that are becoming a standard for VHDL synthesis. It may
also be necessary to include vendor specific libraries to access various vendor spe-
cific features.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
This text is about starting to learn how to design large digital systems. A large use ieee.std_logic_unsigned.all;
part of that activity is knowing how to use and apply electronic design automation
Figure 7.1 Library Declarations
tools including hardware description languages (HDLs) for design specification,
simulation, and synthesis. The library declaration makes the library IEEE visible and the use declarations
This chapter describes the essential VHDL needed for this text. VHDL is used cause the packages std_logic_1164, std_logic_arith, and std_logic_unsigned to be
in this text for designing, simulating, and implementing digital systems at the gate used when referenced. Packages contain useful predefined language elements such
and register transfer level (RTL) of specification, and hence we concentrate on the as standard types and over-loaded arithmetic operators such as arithmetic addition
synthesis subset of the language. VHDL, because it is a concurrent programming (+) and subtraction (-) that can be used with logic valued types such as
language with support for describing circuit delays and structure, can also be used std_logic_vector.
to create abstract high-level models of digital systems. These simulation models,
and those aspects of the language, can be extremely complex and are beyond the Types
scope of this text.
VHDL is chosen because it is an IEEE standard and can be used to write
VHDL defines data representation types, and the scalar and array types include
abstract system-level models to gate level specifications for programming a simple
objects such as integer, real, and bit. For various reasons none of these are quite
field programmable device (FPD). Verilog would also be a good choice, but most
right for describing digital circuit values. Most synthesis tools, and simulation
low cost tools support VHDL and not Verilog. As to other specialized or vendor
models, use the type std_logic from the IEEE library. The type std_logic is a
specific languages that just target FPDs, they are not really any simpler to learn,
resolved type that can model buses by allowing the representation of multiple tri-
and are not sufficient for complex tasks. VHDL will be a language you can use
state drivers driving a signal and is derived from a base type std_ulogic.
throughout your engineering career whether you are programming a 16V8 PLD or
modeling a flight control system.
The following style guidelines should be sufficient to study the problems
posed in this text. These are a minimal synthesis set and will work with almost all
VHDL synthesis tools (with minor modifications). See your tools for additional
supported constructs. This chapter provides general background. Additional lan-
guage details and examples are provided in subsequent chapters.
Essential VHDL 69 70 Digital Engineering with VHDL

TYPE std_ulogic IS ( U, -- Uninitialized library ieee;

X, -- Forcing Unknown use ieee.std_logic_1164.all;
0, -- Forcing 0 use ieee.std_logic_arith.all;
1, -- Forcing 1 use ieee.std_logic_unsigned.all;
Z, -- High Impedance
W, -- Weak Unknown entity example is
L, -- Weak 0 port (A, B: in std_logic_vector(7 downto 0);
H, -- Weak 1 C: out std_logic_vector(15 downto 0);
- -- Dont care MSB, LSB: out std_logic;
); ONE: out std_logic;
TWO: out std_logic_vector(3 downto 0));
Figure 7.2 VHDL Std_logic Values end example;
For modeling of digital systems the type std_logic with it range of signal val- architecture synthesis of example is
ues other than just 0 and 1can better represent the physical behavior of digital begin
systems. For synthesis, where the function of a circuit is defined, as opposed to
modeling the behavior of an existing system, only four of the nine possible values C <= A & B; --Concatenate two 8-bit vectors
-- into a 16-bit vector
are needed. These include the fundamental boolean values 1 and 0, Z to rep-
resent the high-impedance state, and - to indicate a dont care value. The - is MSB <= A(7); --Slice off MSB
the equivalent of a dont care in a K-map. The other values such as a forcing
LSM <= B(0); --Slice off LSB
unknown (X) would never be used in synthesis, though it might appear in simula-
tion due to a design flaw from a driver conflict on a signal. ONE <= 1; -- A constant 1
In this text we will use the types std_logic and std_logic_vector to the near
TWO <= "0010"; -- A constant decimal 2
exclusion of all other types. Std_logic is a scaler (a one bit signal) and
std_logic_vector is an array (or composite or aggregate) of one bit values. end synthesis;
Std_logic_vectors are used to represent buses. Our std_logic_vectors will always Figure 7.3 Std_logic and Std_logic_vector Assignments
have a descending range. That is (N downto 0). The least significant bit (LSB) 20
will be X(0) and the most significant value 2n (MSB) will be X(N). Constant Most synthesis tools will support synthesis of integers when the range is con-
std_logic values are represented by 0, 1, -, and Z, while std_logic_vectors strained by a subtype declaration. In other words, if we declare that an integer sig-
are a string value of 1s, 0s, -, and Z surrounded by double quotes, e.g. nal can only hold values in the range 0 and 15 the synthesis tool can map this onto
"00110010". a 4-bit binary vector (which can represent the decimal values 0 through 15). Using
unconstrained integers will result in a mapping onto a 32-bit vector which will cre-
ate an excessively large solution which will be difficult to simulate, difficult to syn-
thesize, difficult to map to an actual device, and typically is not what is wanted.
While using integer subtypes makes for more readable VHDL, it may require using
conversion functions to convert between the integer subtype and the types std_logic
and std_logic_vector.
Essential VHDL 71 72 Digital Engineering with VHDL

library ieee; synthesis tool might encode the states as binary, gray, or one-hot, converting each
use ieee.std_logic_1164.all; string literal to a unique binary value.
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; library ieee;
use ieee.std_logic_1164.all;
entity ints is use ieee.std_logic_arith.all;
port (a, b: in integer range 0 to 15; use ieee.std_logic_unsigned.all;
sum: out integer range 0 to 15;
sb: out std_logic); entity fsm is
end ints; port ( control: out std_logic_vector(4 downto 0);
reset, clk: in std_logic);
architecture synthesis of ints is end fsm;

--Define a subtype fourbits architecture synthesis of fsm is

subtype nibble is integer range 0 to 15;
--Define three state with an enumerated type
--Declare a signal int_tmp of type nibble type states is (start, run, halt);
signal int_tmp: fourbits; --Create a signal using the enumerated type
signals state: states;
signal bit_tmp: std_logic_vector(3 downto 0);
begin
begin process
begin
--Add a and b and assign to an integer wait until clk=1;
int_tmp <= a + b; if reset = 1 then
state <= start;
--Convert integer to a std_logic_vector control <= "0000";
bit_tmp <= CONV_STD_LOGIC_VECTOR(int_tmp, 4); else
case state is
--Convert std_logic_vector to a integer when start =>
sum <= CONV_INTEGER(bit_tmp); state <= run;
control <= "0011";
--Slice a bit and assign it to a std_logic when run =>
sb <= bit_tmp(3); state <= halt;
control <= "1100";
end synthesis; when halt =>
state <= halt;
Figure 7.4 VHDL Integers control <= "1100";
end case;
It is also possible to use non-numeric types in synthesis. These enumerated end if;
types allow specifying integer values as string literals. They are very useful for end process;
describing states and distinct operations. Descriptive names such as START, end synthesis;
STOP, RUN are easier to understand then binary or integer encodings such as Figure 7.5 VHDL Enumerated Types
"001", "010", and "100". Typically the synthesis tool will encode the enumerated
types for conversion to a state machine depending on its settings. For example a
Essential VHDL 73 74 Digital Engineering with VHDL

Entity Declarations
DESIGN

entity DESIGN is A[7..0]

port( A, B: in std_logic_vector(7 downto 0); B[7..0]
Every digital circuit has input and output ports. VHDL uses an ENTITY dec- DOUT: out std_logic_vector(7 downto 0); DOUT[7..0]
RESET
laration to describe the circuits ports. You can think of the ENTITY declaration as RESET: in std_logic;
CLK: in std_logic); CLK
a block in a block diagram. The ENTITY declares the names of the inputs and out- end DESIGN;
U1
puts, specifies their direction. and defines their type and width.
Figure 7.8 Example Entity Declaration
entity ENTITY_NAME is
port( SIGNAL_NAMES: DIRECTION_MODE TYPE );
end ENTITY_NAME; Lets try to put this all together. The example entity named DESIGN has two
Figure 7.6 VHDL Basic Entity Declaration
8-bit input buses A and B, one output bus DOUT, and two more inputs RESET and
CLK. All but purely combinational circuits will have a clock and reset. Most inter-
Ports, the inputs and outputs of a circuit, have a mode that specifies their direc- esting circuits in this text will be synchronous sequential circuits and will have a
tion. Modes used in this text are IN, OUT, INOUT, and BUFFER. Ports of IN can reset and clock input. So to create most entities for this text simply change the
only be read in the entitys architecture. Trying to write, or assign a value to a port name, the number of ports, their modes, and type of the ports in entity DESIGN to
of mode IN will result in an error. In other words, ports of mode IN can only match the new design problem.
appear on the right hand side (RHS) of an assignment statement. Ports of mode
OUT can only be written, attempting to read the value will result in an error. Ports
Architecture Declarations
of mode OUT can only appear on the left-hand side (LHS) of an assignment state-
ment.
A port of INOUT can be both read and written by the entity and is usually While the entity declaration is used to describe the ports of the digital system,
used for true bi-directional ports. INOUT ports can be driven by other modules the architecture is used to describe the behavior and internal structure of the sys-
and these external values can be read by the entity. BUFFER ports can be written, tem.
and read, but only the value written by the entity can be read. In other words a architecture ARCH_NAME of ENTITY_NAME is
BUFFER is like an OUT tied to an IN. Ports of mode BUFFER can be used to
avoid using an internal signal to store a value, allowing a port to be both a port and SIGNAL_DECLARATIONS;
the output of a register or combinational logic.
begin
SIGNAL_NAME: MODE TYPE;
THE_HARD_STUFF;
Figure 7.7 VHDL Basic Por t Declaration
end ARCH_NAME;
The basic port declaration has a SIGNAL_NAME that is the identifier or name
Figure 7.9 Basic Architecture
of the port. The only thing to remember here is not to use a VHDL keyword (like
"entity" or "IN" or "OUT") or start the identifier with a number. Popular sig- Every architecture has a name (ARCH_NAME) and is associated with an
nal_names might be AIN, Data_out, Clock, and reset. VHDL literals are not case entity (ENTITY_NAME). There is a declarative region between the architecture
sensitive. In other words AIN, ain, Ain, and aIn all refer to the same identifier. The declaration and the BEGIN in which signals (circuit nodes) internal to the compo-
MODE is either IN, OUT, INOUT, or BUFFER, and the type will typically be a nent are declared. While ports on entities are visible to other entities, internal sig-
std_logic scaler or a std_logic_vector. nals are not. After the BEGIN is where the hard stuff is specified. Here is
Essential VHDL 75 76 Digital Engineering with VHDL

where the statements that describe the behavior and structure of the digital system
are declared. The sample architecture shows some basic signal declarations.
Signals are used to connect concurrent operations.
components execute concurrently. In many ways hardware design is the design
of concurrent system. While once the realm of the hardware designer, concurrent
systems design is becoming more a part of software systems, ever more blurring
the line between hardware and software.

architecture synthesis of design is architecture synthesis of example

X
begin X A
signal X, Y, Z: std_logic;
signal tmp: std_logic_vector(7 downto 0); Y --These three statements exeucte simultaneously Y
--whenever X, Y, A, or B change C
begin

--The Hard Stuff Missing TMP Z A <= X AND Y;

B <= X OR Y; B
end synthesis;
C <= A AND B;
These three components execute simultaneously
end synthesis; updating their outputs on any change on their inputs.
Figure 7.10 Sample Architecture
Figure 7.11 Concurrent Statements

Describing Circuit Behavior
At this point the boiler-plate needed for the basic use of VHDL for synthe-
sis has been described. Boiler-plate is the standard stuff for all designs. (As in
steel plate to build a boiler.) We now need to study how to define the behavior and
structure of digital systems in a subset of VHDL. It is important to remember that
VHDL is a large language, used for many different purposes and only a tiny subset
of it is presented in this text. VHDL that might be acceptable to a full VHDL sim-
ulator may not synthesize, or may not produce the hardware implementation you
expect. Unlike programming and compiling a program, different forms of the
same specification will frequently result in quite different hardware implementa-
tions. Synthesis tools require more piloting than compilers to arrive at the desired
circuit implementation, size, and performance.
Concurrent Statements
Concurrent signal assignment statements are the simplest VHDL statements
and are typically used to specify combinational logic. Operators available for our
use include AND, OR, NOT, NAND, NOR, XOR, XNOR, + (binary addition), -
(binary subtraction), and & (concatenation). Basic concurrent signal assignments
can be used to specify basic boolean functions, leaving it up to the synthesis tools
to minimize and optimize the equation.
A <= X + Y;
B <= (M AND N) OR (O AND P);
C <= X & Y;
Figure 7.12 Legal Concurrent Assignment Statements
VHDL is a strongly typed language. The types on the RHS and the LHS must
be the same, and if vectors (arrays), must be of the same length. This makes sense
and helps to avoid design errors. One should not be able to tie a 4-bit bus to an
8-bit bus unless one explicitly resolves the dangling 4 bits.

Unlike programming languages, some statements in a VHDL architecture

execute concurrently, not in sequential order typical of most programming lan-
guages. This is necessary if we are to be able to describe digital hardware. In a
digital circuit consisting of multiple components, all the components are active
simultaneously, updating their outputs whenever an input changes. The hardware
Essential VHDL 77 78 Digital Engineering with VHDL

signal X: std_logic_vector(3 downto 0); A <= X AND Y OR W AND Z; -- AND and OR have the same precedence.
signal Y: std_logic_vector(7 downto 0); -- Parenthesis must be used to indicate
-- the order of evaluation or an error
begin -- will be reported.

Y <= "0000" & X; --Extending a 4 bit bus with zeros. A <= (X AND Y) OR (W AND Z); -- Typically what is wanted

B <= NOT M AND N; --This is the same as ...

Figure 7.13 Concatenating Vectors
B <= (NOT M) AND N; -- as the NOT has higher precedence than AND
Most of the operators like AND, OR, and arithmetic addition + should be -- hence NOT M is evaluated before the AND term.
familiar to you. One that may not have an obvious function is the concatenation
Figure 7.15 VHDL Boolean Operator Precedence
operator &. Concatenation allows signals to be combined into larger compos-
ites (bigger arrays or buses). The opposite, slicing apart a bus, is implied by the At this point with simple signal assignment statements we can write boolean
language. equations in VHDL, and even arithmetic equations using the overloaded + and
- operators, but we are still forced to derive the boolean equations manually.
Combine two buses into one larger bus
The advantage of VHDL comes from using complex VHDL concurrent signal
A(0)
architecture synthesis of example is assignment statements and letting the synthesis tool derive the implied boolean
signal A, B, C: std_logic_vector(3 downto 0);
A(1) signal X: std_logic_vector(7 downto 0); (logical) equations and their optimized implementation.
A(2) X(0)
begin
A(3) X(1)
X(2) X <= B & A;
X(3) C <= X(7 downto 4); Concurrent Signal Assignment Statements
X(4)
end process;
X(5)
B(0) X(6)
B(1) X(7)
We will use two forms of concurrent signal assignment statements. The condi-
B(2) tional signal assignment statement allows the expression of arbitrary if-then-elsif-
B(3) Slice off a part of a bus
C(0)
then-else-end conditionals in concurrent signal assignment statements. This state-
C(1) ment is the equivalent of an if statement within a VHDL process statement. (The
C(2)
C(3) process statement is discussed later.)
Figure 7.14 Concatenation and Slices

An important issue in writing boolean equations in VHDL is the precedence of

operators. This determines how the language associates operators. If two opera-
tors, such as AND and OR, have the same precedence, the association must be
made clear by the use of parenthesis. NOT has a higher precedence than AND and
OR so that it associates with the nearest literal without parenthesis. Of course
using parenthesis even when not required wont hurt, and will make the equation
more readable and less prone to errors.
Essential VHDL 79 80 Digital Engineering with VHDL

A <= B when X = 1 --Process equivalent form X

with X select A <= B when "00", --Process equivalent form X
else C when Y = "00" B C when "01",
else D; process
1 D when others; process
begin C 1 A
if X = 1 then MUX begin B
D MUX 0 case X is 00
A <= B; 0
C
elsif Y = "00" then when "00" => A <= B; 01 A
when "01" => A <= C; D MUX
A <= C; Y 10

else when others => A <= D; D

NOR 11
A <= D; end case;
end if; end process;
end process;

Figure 7.16 Conditional Signal Assignment Statement Figure 7.18 Selected Signal Assignment Statement

SIGNAL <= EXPRESSION when CONDITIONAL with STATIC_EXPRESSION select SIGNAL <= EXPRESSION when CHOICES,
else EXPRESSION when CONDITIONAL EXPRESSION when CHOICES,
else EXPRESSION; EXPRESSION when others;,

Figure 7.17 General Conditional Signal Assignment Statement Figure 7.19 General Selected Signal Assignment Statement

The general form of the conditional signal assignment consists of expressions The selected signal assignment statement typically tests a signal (in this case
to be assigned to the signal and arbitrary conditions which determine when each X) and assigns values to a target (in this case A) based on the possible values of X.
expression is assigned to the signal. This statement looks and acts like an arbitrary The difference between the conditional statement (if-elsif-else) and the selected
if-elsif-else statement, and it has a shortcoming with respect to hardware. An if- signal assignment is that the selected signal assignment statement enforces the
elsif-else statement implies a priority. If two conditions are true, the first in the list mutual exclusion of the conditions (because the conditions are choices based on a
is executed. This results in more hardware to enforce the order of execution prior- single literal and the values it can hold), and all the possible values of the literal
ity, unless the conditions are mutually exclusive in which case a CASE statement must be covered either explicitly or with the others clause. The true advantage
can be used. of the conditional statement is it uses less hardware as no priority of conditions
needs to be enforced. Both the conditional signal assignment statement and the
Another problem is that if the statement does not have a trailing else the hard-
selected signal assignment statement allows the direct expression of a boolean truth
ware generated will have a latch generated. The reason is quite simple. Without an
table in VHDL.
else the signal being assigned may not be assigned a value every time the if-elsif is
executed. This implies that the signal must hold it previous value and hence a latch
is needed in the digital circuit to faithfully replicate that behavior. Many synthesis
tools enforce the else in conditional signal assignment statements, some do not.
Either way, if you use a conditional signal assignment statement make sure to
include the final else to ensure that combinational logic is generated.
While the conditional signal assignment is like an if-elsif-else statement the
selected signal assignment statement is equivalent to a case statement.
Essential VHDL 81 82 Digital Engineering with VHDL

A B C | Z with ABC select Z <= 0 when "000", Complex Behavior

--------- 1 when "001",
0 0 0 | 0 0 when "010",
0 0 1 | 1 0 when "011", At this point we can write an entity, create an architecture, and even describe
0 1 0 | 0 1 when "100", combinational circuits in VHDL. But this does not allow us to describe more com-
0 1 1 | 0 1 when "101",
1 0 0 | 1 0 when "110",
plex behaviors associated with sequential circuits, nor to take full advantage of the
1 0 1 | 1 1 when others; synthesis systems ability to generate the digital circuit implementation from a
1 1 0 | 0 complex VHDL description using familiar programming constructs.
1 1 1 | 1
Within the body of an architecture the general form of concurrent statement is
Figure 7.20 Truth Tables in VHDL the process statement. The process statement is the general method for the expres-
Conditionals in VHDL test the relationships between objects such as signals, sion of concurrency in VHDL. The process statement contains statements that
ports, and constants. The usual operators are available including equality (=), execute in sequential order and in zero time. This allows specifying complex
inequality (/=), less than (<), less than equal (<=), greater than (>), and greater than behaviors of components above the boolean equation level. Any concurrent signal
or equal (>=). Comparisons can be between signals or between signals and literals assignment statement (as just described) can be expressed as process statement.
(constants). The IEEE libraries allow the comparison of std_logic_vectors with Conditional and selected signal assignments statements are actually a shorthand for
integer literals and signals. a corresponding process with an if-elsif-else or case statement within a process
declaration.
signal X: std_logic_vector(7 downto 0);
signal Y: std_logic_vector(7 downto 0);
The process statement has the general form of a process declaration, a declara-
tive region for variables local to the process, and then a statement declarative
signal A: std_logic; region. Of all the VHDL constructs we will use in this text, the process statement
signal B: std_logic; will be the most simplified. It will be used for describing all clocked circuits, and
X = "00001000" --Is X equal to 8 complex combinational circuits. It is also how concurrency is expressed in VHDL,
with multiple processes within a single architecture expressing the concurrency of
X /= 255 --Is X not equal to 255 decimal digital hardware.
X > Y --Is X greater than Y process
--Variables are declared here in the process declarative region
(X < 16) OR (X > 32) --Is X less than 16 or greater than 32 begin

A = X(0) --Compare two bits --Sequential statements are here in the statement declarative region

(A AND B) = 1 --Compare a boolean equation to a constant end process;

Figure 7.22 Process Declaration
Figure 7.21 Conditional Expressions
Essential VHDL 83 84 Digital Engineering with VHDL

architecture count of synthesis is

CLOCK
signal A: std_logic_vector(3 downto 0);

begin
Register
process A+1 A
begin
wait until clk=1;
+
if reset = 0 then
A <= "0000"; "1"
else
A <= A + 1;
end if; RESET
end process;
Figure 7.24 Synthesized Counter
end synthesis;
Figure 7.23 Simple Counter Process An important point is to notice what has happened to the signal A. It has
become a register. This makes sense in terms of the semantics of VHDL and those
The above process reads exactly as one expects and the synthesis tool will cre- of a clocked circuit. Signals hold their values, and so do registers. So while a sig-
ate the expected circuit. This process waits until the clk goes from 0 to 1 then nal is a node in the circuit, in this case the synthesis system places a register driv-
executes the sequential statements. Notice that the process has only one wait state- ing the node A. Hence the signal A and the register that holds the value of A are
ment and it is the first statement. Do not try to use more wait statements or use one in the same. The synthesis tool inferred a register from the VHDL syntax and
them elsewhere in the process with an RTL level synthesis tool. (Behavioral syn- semantics. Not all signals become the output of registers. If A was simply
thesis tools can support multiple wait statements.) The VHDL (or circuit) tests the assigned a value of a combinational equation, and there was no wait until
value of reset, and if it is 0, A is cleared, else A is incremented by 1. The follow- clk=1 statement, it would be that function and appear to be the output of the cor-
ing circuit shows one possible implementation. responding gates. The synthesis tool inferred a register from the VHDL syntax and
semantics.
Essential VHDL 85 86 Digital Engineering with VHDL

Synthesis infers a flip-flop from the wait statement.

use a different style for a clocked process. The asynchronous reset puts the reset
LHS is the output Q condition first in the if-elsif statement giving it priority over the clock, just as in a
process LHS is the output Q asynchronous clear flip-flop.
begin
wait until clk = 1; process(clk,reset)
Q --Dont use variables
Q <= not Q and not RESET; RESET D Q
begin
end process; CLK if reset=0 then

RHS of the signal assignment statement is the D input, -- Initial conditions for registers

process
elsif (clkevent and clk=1) then
begin X
C
C <= not X and not Y; Y B -- Behavior of the circuit when not in reset.
B <= C and Z;
Z
end process; end if;
end process;
Figure 7.27 Asynchronous Reset
Without a wait statement combinational logic is generated
Figure 7.25 Inferring Flip-flops At this point you might notice that synthesis tools depend on "style" to infer
much of the function of the circuit. The condition (clkevent and clk=1) is a sam-
ple of full VHDL. The clause clkevent is true when clk has just changed value
process (0 to 1 or 1 to 0) and clk=1 tests for clk being one. Together these two
begin statements test if clk has just changed from 0 to 1.
wait until clk=1; For the synthesis tool (clkevent and clk=1) is effectively just style keywords
that directs it to implement the design using positive edge-triggerd flip-flops. The
if reset = 0 then -- Reset either active high or low (1 or 0)
form (clkevent and clk=1) does simulate correctly (before synthesis in a VHDL
-- Initial conditions for registers simulator) and so is used for synthesis. As with the wait until clk=1; the
(clkevent and clk=1) can only appear once as the elsif condition. No else part
else is allowed. Negative edge-triggered flip-flops can be indicated with wait until
-- Behavior of the circuit when not in reset. clk=0; or (clkevent and clk=0).
Style is very important to VHDL synthesis. Arbitrary VHDL may produce an
end if;
end process;
error or worse synthesize to an unexpected and unwanted circuit. On the other
hand, particular style guidelines may be needed by a particular tool to take advan-
Figure 7.26 Generic Clocked Process
tage of a particular tools capability or technology. On the other hand if you are
The use of an explicit wait statement implies an synchronous reset. This is fre- familiar with programming then feel free to experiment. For example a slight mod-
quently not a problem as many small FPDs dont support asynchronous resets ification of the VHDL for a asynchronous reset allows it to be used for a syn-
(their flip-flops simply dont have that capability). To specify an asynchronous chronous reset simply by making the (clkevent and clk=1) the if conditional for
reset and make use of the global asynchronous resets available in FPGAs one must an if-then-end statement.
Essential VHDL 87 88 Digital Engineering with VHDL

process(clk,A) process
begin begin
if (clkevent and clk=1) then
if reset = 1 then wait until clk = 1
A <= "0000";
else if reset = 0 then
A <= A + 1; X <= "0000";
end if; else
end if; if A = "00" then
end process; X <= X + 1;
else
Figure 7.28 Alternative Synchronous Reset X <= X;
end if;
end if;

Sequential Statements end process;

Figure 7.30 If Conditional in a Process

VHDL has the full range of sequential statements found in any programming Use if statements freely in clocked process. You can also nest them as neces-
language including IF, CASE, and various forms of LOOP. We will not use the sary. You get what you expected. A register to hold X that is only incremented by
LOOP constructs much (though they can be synthesized if the loop values are con- one when A = "00". But things go awry if the if conditional does not cover all
stants). Loops in VHDL are typically used for describing combinational logic and cases and the circuit is not clocked.
implied structure. VHDL also has GENERATE statements for the conditional gen-
process(A,X)
eration of structural descriptions. Advanced synthesis tools can convert general for
begin
loops into sequential machines by inferring and creating the state machine to if A = "00" then
implement the loop counter and control logic. X <= X + 1;
elsif A = "01" then
if conditional then X <= X + 2;
--sequential statements end if;
elsif conditional then end process;
--sequential statements
else Figure 7.31 Improper IF
--sequential statements
end if; What happens with an improper if that does not cover all cases is that when
A is not equal to "00" or "01" no value is assigned to X. Since the value of X is not
Figure 7.29 If Conditional
defined for all values of A it must hold its value for values of A other than "00" and
"01". Hence while this process does not have a clock it still implies a register and
the synthesis tool builds a latch controlled by the value of A (and not the clock). It
will latch X on A = "00" or A = "01". While expecting a combinational equation,
one ends up with an unclocked transparent latch controlled by combinational logic,
and very unpredictable behavior.
Essential VHDL 89 90 Digital Engineering with VHDL

process(A,X) case X is
begin when "00" => Z <= "001";
if A = "00" then when "01" => Z <= "111";
X <= X + 1; when "10" => Z <= "011";
elsif A = "01" then when others => Z <= "101";
X <= X + 2; end case;
else
X <= X + 4; Figure 7.34 Case Statement
end if;
end process;
The above case statement simply implements a truth table of input variables
X(1) and X(0) and outputs Z(2), Z(1), Z(0). The use of the others condition is
Figure 7.32 Proper IF Covers Every Case
required for std_logic_vectors. While the case will typically explicitly cover all the
The above unclocked proper if process will generate a purely combinational combinations of 1s and 0s, std_logic defines another seven values (Z, -, X,
circuit. Notice the "else" condition. X is assigned a value for any possible execu- U, L, H, W). These other choices are covered by the others.
tion of this process. The following process achieves the same result, in a much
more round about way, by creating a variable, assigning a value to it outside of the
if, changing the value if the if statement executes, and then finally assigning it to
the target signal X.
process
variable tmp: std_logic_vector(1 downto 0);
begin

tmp := X + 4; --tmp gets unconditionally assigned

if A = "00" then
tmp := X + 1;
elsif A = "01" then
tmp := X + 2;
end if;

X <= tmp;

end process;
Figure 7.33 Proper IF with Variables

In general, IF statements should be used with care when specifying combina-

tional logic. First they add logic for enforcing the implied priority of an IF state-
ment in addition to the possibility of unintended latches. Instead use a CASE state-
ment when possible. It will enforce that every input is covered ensuring a combina-
tional circuit in unclocked processes.
Essential VHDL 91 92 Digital Engineering with VHDL

case Q is
expresses the general form of the algorithm and automates the generation of the
if sel=1 then
A <= X; when "00" => Z <= 1; equation. The synthesis tool effectively unrolls the for loop, generating the final
else when "01" => Z <= 0; value of tmp.
A <= Y; when "10" => Z <= 1;
end if; when "11" => Z <= 1;
when others => null; process(d0, d1, d2, d3, d4, d5, d6, d7)
end case;
SEL Q variable tmp: std_logic_vector(2 downto 0);
variable ins: std_logic_vector(7 downto 0);
X 1 00
1
A 0 01 Z begin
Y 1 10
0 tmp := "000";
1 11
ins := d0 & d1 & d2 & d3 & d4 & d5 & d6 & d7;

if M = 1 then if SIG = "11"then for I in 0 to 7 loop

B <= TMP1; D <= X1; tmp := tmp + ins(I);
elsif N = 0 then end if; end loop;
B <= TMP2;
else cnt <= tmp;
B <= TMP3; X1 D Q D
end if; end process;

N --Alternative equivalent concurrent statement

M SIG(1) cnt <= ("000" & d0) + ("000" & d1) + ("000" & d2) + ("000" & d3)
CP + ("000" & d4) + ("000" & d5) + ("000" & d6) + ("000" & d7);
TMP2 SIG(0)
0
0
TMP3 B Figure 7.36 Count Ones Process
1
TMP1 Another example is a simple parity checker of 2-input XOR gates. Here the loop is
1
again unrolled to generate the final value of the variable result and the signal par-
Figure 7.35 Example Circuit Translations ity_out.

While we wont make much use of loop statements a couple examples are
worth considering. An interesting problem is to express the function that counts the
number of ones in an input array. Assuming an 8-bit input, if the pattern is
"00100010" then the output should be 2. If the input pattern is "11110000" then the
output is 4.
Such a function is readily described with a truth table, but is cumbersome to
generate manually. Instead a FOR LOOP can be used to sum the bits. The for loop
simply calculates the sum of the inputs as tmp := ins(0) + ins(1) + ins(2) + ins(3) +
ins(4) + ins(5) + ins(6) + ins(7);. The advantage of the FOR LOOP is that it
Essential VHDL 93 94 Digital Engineering with VHDL

process(input) 0
variable result : bit;
begin INPUT(0)

result := 0;
INPUT(1)
for k in 0 to 3 loop
result:= result xor input(k);
INPUT(2)
end loop;
PARITY_OUT
parity_out <= result; INPUT(3)

end process; For Loop Generated Form

Figure 7.37 For Loop Parity Checker

INPUT(0)

INPUT(1)

PARITY_OUT

INPUT(2)

INPUT(3)

Simplified Form
Figure 7.38 Parity Checker Circuit

Structural Design

In this course our VHDL designs are generally small enough that the entire
design is readily described by a single entity/architecture pair with at most several
processes. But as in schematic capture or programming there comes a point when
breaking the design into separate modules makes the problem easier to solve and to
understand. It also supports repeated reuse of a module. Divide and conquer.
VHDL supports the structural design of digital systems with several language
constructs. First there are packages that can contain functions and procedures. The
package is intended to hold types, functions, and procedures common to a design.
But these simply allow organizing the language, and do not directly allow
Essential VHDL 95 96 Digital Engineering with VHDL

expressing the structure of the digital system under design. entity example of
The basic structural statement is the component instantiation statement that port ( AIN, BIN: in std_logic_vector(7 downto 0);
DREG: out std_logic_vector(7 downto 0);
names the instance, declares which entity is being instantiated, and associates sig- CLOCK: in std_logic;
nals and ports with the ports on the entity. RESET: in std_logic);
end example;

EXAMPLE architecture structural of example is

AIN
BIN
--Required for VHDL 1987
DREG component adder
CLOCK
RESET port(A, B: in std_logic_vector(7 downto 0);
S: out std_logic_vector(7 downto 0));
end component;

--Required for VHDL 1987

component reg
port( DIN: in std_logic_vector(7 downto 0);
ADDER
DOUT: out std_logic_vector(7 downto 0);
AIN RESET: in std_logic;
A REGISTER CLK: in std_logic);
TMP
SUM DIN end component;
CLK DOUT DREG
BIN B
RESET signal TMP: std_logic_vector(7 downto 0);

begin
CLOCK
--VHDL 1987 Instantiation
RESET U0: adder port map (AIN, BIN, TMP);
U1: reg port map (TMP, DOUT, RESET, CLOCK);
Figure 7.39 Structural Design --VHDL 1993 Direct Instantiation
U0: entity work.adder(synth) port map (AIN, BIN, TMP);
U1: entity work.reg(synth) port map (TMP, DREG, RESET, CLOCK);
Assuming an adder and a register entity are available they can combined by
creating a new entity/architecture pair that specifies how they are to be connected
or wired together to build an incrementer. end structural;
Figure 7.40 Structural Design

A bit of bother is the component declaration (VHDL-93 does not require this
as it supports direct instantiation) that is required in the architecture (or a support-
ing package) that specifies the ports on the instantiated entity (notice that the com-
ponent declaration contains the same information as the entity declaration.)
Essential VHDL 97 98 Digital Engineering with VHDL

Basic Circuit and VHDL Semantics entity simple is architecture synthesis of simple is
port(A,B,CLK: in std_logic; signal TMP: std_logic;
X: out std_logic); begin
end simple;
At this point you have been introduced informally to the syntax of VHDL. process(A, B)
begin
This section attempts to informally present the behavior, or semantics, implied by TMP <= A OR B;
VHDL. Together these informal introductions should allows you to write simple A
end process;

VHDL descriptions of digital circuits that will produce the intended synthesized TMP
circuit behavior. B
X
The entity declaration as mentioned before simply names and describes the D Q
CLK process
mode (in, out, inout, buffer) and type (std_logic, std_logic_vector) of the ports of begin
wait until clk=1;
the circuit. It does not impact the behavior of the circuit directly. The architecture X <= TMP;
is where the behavior is described. The biggest obstacle to writing synthesizable end process;

VHDL is that in VHDL same behavior can be described in multiple ways. Com- end architecture;

plicating the matter even more is that different, functionally equivalent, VHDL
descriptions when given to a synthesis tool can produce different implementations
that can differ in size and performance.
Digital systems are concurrent systems. In other words a systems components
are all simultaneously active. VHDL is a concurrent programming language and
concurrency is expressed by the use of multiple processes. In other words, pro-
cesses correspond to the simultaneously active components in a digital circuit.
These processes can have arbitrarily complex behaviors. Single threaded behaviors
are described by a series of sequential steps. Hence while processes all execute
concurrently the statements within a process execute in order, but in zero time.
Figure 7.41 Concurrency
When writing VHDL the concurrent operations of the digital system are
described using processes, concurrent signal assignments, and component instanti-
ation statements within an architecture body. Processes allow the description of
complex behaviors using sequential statements. Concurrent signal assignments are
a shorthand for simple behaviors. And component instantiation statements allow
describing systems in terms of the interconnection of entities (which consist them-
selves of processes, concurrent signal assignment statements, and component
instantiation statements).
Any digital system that can be described in VHDL can be described as a col-
lection of processes. Structural VHDL is simply a way of organizing the design
such that processes reside in separate architectures. But the design could be col-
lapsed into a single architecture containing all the processes and signal to intercon-
nect them. All concurrent signal assignment statements have an equivalent process
form.
Processes, concurrent signal assignments, and component instantiation state-
ments communicate via signals within an architecture. Signals are the wires in
VHDL that connect together the digital components described by VHDL pro-
cesses, concurrent signal assignments, and component instantiation. Ports are also
signals, and allow entities to communicate when they are attached to signals when
instantiated within another architecture.
Essential VHDL 99 100 Digital Engineering with VHDL

When describing systems for synthesis, circuit delays are determined by the
target technology, and hence when writing VHDL for synthesis signal assignment
statements never include a delay assignment. But all digital circuit elements have a
delay, even if it is infinitesimally short. This 0ns delay (delta delay) has little
impact on writing VHDL for synthesis but most be included so that all circuits will
be physically realizable. Physical circuits always have have finite delays. Zero
delay circuits, and circuit designs that depend on zero delay components could
never be built. A finite non-zero delay corresponds to a unit delay.
The only time this non-zero signal assignment of RHS values to LHS values is
noticeable is in processes where statements are evaluated sequentially. In this case
multiple assignments always read the old value of a signal, never the new value.
This has little consequence in combinational processes as the values will take on
the new value in two delta delays and the circuit will behave as if the assignment to
the signal occurred in zero time. In other words the combinational logic generated
will be correct.
The semantics of signals in VHDL is described by the simulation semantics of
the language. Signals only take on their new values when the process has sus-
pended during simulation. A process suspends when it reaches a wait statement.
Either the explicit wait such as wait until clk=1 or an implicit wait defined by a
sensitivity list process(A,B,CLK). The sensitivity list implies a wait statement
as the last statement in a process as wait on A,B,CLK. This notion of a process
waiting on signals works for both simulation and as a good model of how digital
circuits operate. The concurrent components of a digital system wait for an change
on an input, and then update their outputs.
VHDL also support variables within processes. These do take on new values
immediately. Typically variables are used to generate intermediate or temporary
values within process. Variables should be used carefully as unless unconditionally
assigned will generate a register to hold the value between invocations of the pro-
cess. This can cause the variable to behave like a signal, defeating its use, and cre-
ating unintended registers.

A
Always at least one delta delay X
B D Q
D Q Y
A C
X
B Y

C CLK

process(A,B,C) process
begin wait until clk = 1;
X <= A AND B; X <= A AND B;
Y <= X AND C; Y <= X AND C;
end process; end process;

Implied wait

Figure 7.42 Signal Assignment Delays

For clocked processes the result is quite different. In combination with the
non-zero delay and the inference of flip-flops it becomes clear the Y is working
with the old value of X. (The previously stored value of X). One way to under-
stand this is that X does not take on a new value until a delta delay after the clock 0
to 1 transition and is to late to be assigned to Y. This behavior is identical to the
behavior of flip-flops. Not matter the technology the output of the flip-flop does not
change until after the clock edge and the output of a flip-flop is delayed by a full
clock cycle when driving the input of another flip-flop.
Essential VHDL 101 102 Digital Engineering with VHDL

Common Mistakes
-- Multiple Concurrent Signal Assignments -- Multiple Concurrent Process Signal Assignments
architecture syn of conflict is architecture syn of conflict is
begin begin
1) Getting fancy. Keep your VHDL simple. If you are lost draw a block diagram A <= X + Y; Adder drives a value on A
A <= X - Y; process(X, Y)
and then write the VHDL for each block as a process in an entity/architecture end synthesis;
Subtracter drives a value on A
begin
pair connecting the processes with signals. A <= X + Y; Adder drives a value on A
end process;
2) Being too simple. Remember digital systems are concurrent systems. Use Adder drives a value on A
process(X, Y)
multiple processes and concurrent signal assignment statements to break up begin
X A <= X - Y; Subtracter drives a value on A
the behavior of your circuit. A typical use of multiple processes and current end process;
statements is to separate sequential blocks from combinational blocks. Y
+ Value of A is unknown end synthesis;

3) Forgetting your boolean algebra - A NAND B NAND C is not equal to NOT A

(A AND B AND C). X

4) Precedence - VHDL does not assign precedence to the AND and OR opera- Y
-
tors. Hence given the equation A AND B OR C AND D you will get a com-
piler error. Parenthesis must be supplied. You will likely want (A AND B) OR
Subtracter drives a value on A
(C AND D).
5) Duplicate assignments - In this course we can only have one concurrent signal Figure 7.43 Signal Assignment Conflict
assignment to a signal or port. If two drivers assign a common node in a cir-
cuit an error will occur both in the VHDL simulation and in the actual circuit.
This is a very common error. Outputs cannot be connected directly together.
This does not work in VHDL or in digital logic at the RTL level. You must
use a multiplexer or a tri-state bus controlled by a conditional to enforce
mutual exclusion on the shared signal. A signal can be assigned repeatedly in
a single process, but not in multiple processes.
Essential VHDL 103 104 Digital Engineering with VHDL

Multiplexer and control signal
enforces mutual exclusion so
only adder or subtracter drives
signal A
CON
Dont assume the synthesis tool will make obvious optimizations. If you want
Tri-state drivers and control signal
a particular implementation you must be explicit. Either in behavioral VHDL
enforces mutual exclusion so or by using a structural implementation.
only adder or subtracter drives
signal A
CON

Adder drives a value on A Adder drives a value on A if SEL = 1 then TMP <= Y when SEL = 1 else Z;
A <= X + Y; A <= X + TMP;
X X
else
A <= X + Z;
Y
+ Y
+ end if;
A
A
SEL
X X X

Y
- Y
-
+ Y
0
TMP
Subtracter drives a value on A Subtracter drives a value on A Y 0
Create two tri-state drivers
A
Multiplex values onto A

A <= A+B when CON=1 else A-B;

to mutiplex values onto A
X 1
Z 1
+ A

A <= X+Y when CON=1 else "ZZZZ"; X

Figure 7.44
A <= X-Y when CON=0 else "ZZZZZ";
Multiplexer and Tri-State Buses +
Z
6) Unintended latches and flip-flops - A common problem is the creation (or
insertion) of latches and flip-flops. Combinational latches typically arise when SEL
signals are not assigned values for all possible execution paths of a process or
Figure 7.45 Unintended Hardware
concurrent signal assignment statement. To avoid a latch and make sure that
every signal is assigned a value under all execution paths, use a case statement
or selected signal assignment statement, use an else part for if statements, or
assign the signal a value unconditionally before any conditional assignment.
Unintended flip-flops can also arise in clocked processes. All signals and vari-
ables appearing on the LHS of an assignment statement in a clocked process
will be assigned to a flip-flop unless the signal or variable is unconditionally
assigned a value.
7) Unintended hardware - In the following example equivalent behaviors result in
quite different implementations. Both cause A to be assigned either the value
X+Y or X+Z but the first uses two adders while the second uses one adder.
Essential VHDL 105 106 Digital Engineering with VHDL

Basic Rules The use of variables does not ensure the generation of combinational logic. The
same rules as for signals must be observed.
Always include the library and use declarations.
Understand the capabilities of your target technology and dont ask through
Use the std_logic and std_logic_vector types. No need to get fancy with entity your VHDL synthesis system do more than it can. Remember you are describ-
declarations. ing hardware that consists of basic gates, registers, adders, and counters.

Adhere to the style guidelines.

Use the architecture declarative region to declare signals.

Use case statements instead of if statements.

Simple combinational circuits should use concurrent statements.

Signals in unclocked processes must be assigned a value for every possible

execution sequence of the process to avoid unintended latches.

Use case statements for combinational logic.

If statements when used for combinational logic must include an else part to
ensure all signals are assigned a value under all possible execution sequences of
the if conditional.

Use a process for clock circuits.

Use Wait until clk =1; for a synchronous reset.

Wait until clk =1; must be the first statement in a process and can only
appear once.

Use (clkevent and clk=1) for asynchronous resets.

(clkevent and clk=1) must either be the only conditional of an if-then-end

statement, or must be the elsif conditional of a if-then-elsif-then-end statement.