Simple Entities and Architectures

Dr DC Hendry

January 2006

1 Entity Declarations

The entity declaration gives a name to the design and tells us the signals which are input
and output from the design. Each such signal is given a name and the type of that signal is
given. By type here is meant a choice from BIT, INTEGER or for example BIT VECTOR. This
is similar to the different types which are present in a language such as C, types such as int
or float.

First consider a design which has three input signals, A, B and C, and two output signals X
and Y. The design will be named example2.

Let us note now that VHDL is case insensitive, thus the signal X and the signal x are one
and the same. Here is the code for a suitable entity declaration for this design:

entity example2 is
port(
A, B, C : in bit;
X, Y : out bit);
end entity example2;

The list of input signals, A, B and C are followed by the keyword in, indicating that these
are input signals to the design. For output signals the keyword out is used. Each signal is
of type BIT. Once these signals are declared within the entity declaration, they are available
within the architecture body. The input and output signals can be given as lists as in the
example above, or individually, as in the next example:

entity example2 is
port(
Inputs
A : in bit;
B : in bit;
C : in bit;
Outputs
X : out bit;
Y : out bit);
end entity example2;

Here I have included a comment, -- Outputs, to indicate the start of the list of output
signals. This latter style is usually used with more complex designs as the readability of the
1.1 GENERICs EG/ES 3560

code is improved. It is usual to first list the input signals (and among these first of all list
the clocks), then the outputs.

Beware of the final line of the entity declaration. I have finished the entity declaration with
end entity example2. This is acceptable syntax for VHDL-93, not for VHDL-87. As such
you will need to indicate to many VHDL tools that VHDL-93 syntax is in use, with for
example Cadences NC-VHDL, use the command ncvhdl -v93. The corresponding syntax
in VHDL-87 would be simply end example2.

1.1 GENERICs

Certain designs in VHDL may be used to represent a range of components which differ only
in some manner which may be represented by an integer. For example, it is possible to
use a single design to represent a 2 to 1 multiplexor or a 10 to 1 multiplexor. We would
actually design an N to 1 multiplexor and indicate the value of N when we use the design
as a component in a larger design.

Such integers are called generics in VHDL. Here is an example of such a design (its not
complete, well see to that later):
entity example3 is
generic(
N : integer;
M : integer);
port(
..
.
);
end entity example3;

Note that no direction, such as in or out is required. Although types other than integer
may be used, there are good reasons for limiting ourselves to using integers only (as yet,
most synthesis tools support only integer generics).

2 Types BIT and BIT VECTOR

The signals used in our examples have all been of type BIT. Signals of type BIT may take
one of two values only, 0 or 1. Note that when we write these values in our programs
we must include the enclosing quotes. Thus 1 is a value that a signal of type BIT may
assume, whereas 1 is a value that a signal of type integer may assume. Thus as assignment
to the signal X above of the value 1 would consist of:
X <= 1;

Very often we wish to work with signals which do not consist of single bits, but consist of
a number of bits, for example an address bus or a data bus. A possibility then is to use
type BIT VECTOR. This permits the use of an array of bits. Consider an input signal which
consists of 32 bits. This may be declared as either:
address : in bit vector(31 downto 0); or
address : in bit vector(0 to 31);

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Within code the individual bits may then be referred with expressions such as address(1)
<= 0 and similar. The use of the downto form is prevalent, and is the form you should
use. You may also assign the entire vector in one statement if you wish, using statement
such as:

address <= 0111000. . . . .1101;

(its possible in fact to use hexadecimal here!). There are a large number of mechanisms for
handling vectors in VHDL, some of which we will see later.

A useful type which can be used while designing at a high level is the type integer. While
this has limited applicability for synthesis, it is often used for simulation only designs.

3 Architecture Bodies

The architecture body provides a mechanism for describing the operation of the design.
For a combinational logic design this will provide a description of how the outputs may
be computed from the inputs. For a complex design it is likely to be advantageous to
first describe the design at a very high level (c.f. Levels of Abstraction, Lecture 1 ). When
this description is complete, a more detailed design may then be provided at a lower level,
perhaps a level at which a synthesis tool may complete the design down to logic gate level.

Thus more than one architecture body may describe the same design.

This is the (very) general format of an architecture body:

architecture rtl of example4 is

List of Architecture Declarations

begin

List of Concurrent Statements

end architecture rtl;

In this example the designer has chosen the architecture name rtl presumably to indicate
that the design may be read by a synthesis tool.

The name of the architecture in this case is rtl, a name which the designer can choose.
Architecture names however are generally chosen from a small set of accepted names which
indicate the form of description used, well return to this later.

3.1 Architecture Declarations

Within the architecture declarations we may declare a wide variety of objects. These include:

Signals to be used within the architecture (in addition to those signals in the port list
of the entity declaration).
Components, that is other designs, which will become a subcomponent of this design.

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Constants to be used within the design.

Functions and procedures.
User defined types.

The first of these, signal declarations, allows the use of additional signals within the archi-
tecture. The general format is:

signal <signal name(s)> : <type> ;

Examples:

signal wireA : bit;

signal opcode : bit vector(7 downto 0);
signal r, s, t : bit;

A further form available is:

signal <signal name> : <type> := <initial value> ;

Examples:

signal counter : integer := 0;

If a signal is not given an intial value, a default is defined for simulation. This is 0 for
signals of type BIT and 0 for signals of type integer. Do NOT write designs that rely on
signal initialisation by this mechanism. Such initialisation is not supported by synthesis
tools.

3.2 Concurrent Statements

Following the begin keyword of the architecture body there follows a list of concurrent
statements. There are a number of such statements all of which may executed concurrently.
We shall see what this means when we discuss the simulation semantics of VHDL in a
later lecture. For the moment lets just note that due to these semantics, the order of the
concurrent statements is immaterial.

The simplest concurrent statement is the concurrent assignment statement, which is in

general:

<signal name> <= <expression> ;

where <expression> must return a value of the appropriate type. The expression may be
built up with a variety of operators depending upon the type of the signals involved. For
integers the usual operators, +, -, * and / are available. For signals of type BIT the available
operators include:

or for logical or.

and for logical and.

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nor for logical nor.

nand for logical nand.
xor for logical exclusive or.
xnor for exclusive nor (only available with VHDL-93).
not for logical inversion.

Examples:

x <= a or (c and d);

y <= e and f and g;

z <= ((not e) or g) and a;

Note that round brackets are needed to determine the order of evaluation of operators.
An exception to this rule is then the same operator appears twice in succession and that
operator is associative.

4 The IEEE 1164 Package

All of our signals so far have been of type BIT or BIT VECTOR. The VHDL language incor-
porates a simple mechanism which allows any designer to create their own types as needed.
Experience with such additional types, and how they could be used for synthesis, led to the
establishment of the IEEE standard 1164. This replaces type BIT with the type std logic,
and the type BIT VECTOR with the type std logic vector.

To access this package we need to add the following to our designs before the start of each
entity declaration.

library ieee;
use ieee.std logic 1164.all;

A signal of type std logic can assume more values than just 0 or 1. These additional
values can be used to represent a variety of conditions, such as an unknown value (when
a circuit has just been powered up for example), an indeterminate value (when the output
of two gates is tied together for example), and dont cares (to denote for example that the
output of a circuit doesnt matter in a certain situation). We shall not pursue this in detail
here however. Be aware simply, that while you will find designs that use types BIT and
BIT VECTOR, you should use types std logic and std logic vector. Here is an example
entity header using IEEE 1164:

Types BIT and BIT VECTOR are seldom used, instead the equivalent types from the IEEE

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1164 Package are used.

library ieee;
use ieee.std logic 1164.all;

entity parity is
generic(
N : integer);
port(
packet : in std logic vector(N 1 downto 0);
parityBit : out std logic);
end entity parity;

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