Name: Pawar Pragati Somnath

Branch & Year: E&TC (3rd)

Roll No. 01
Subject: Digital Design
Lab Expt. No. 02
Aim: To perform simulation and synthesis of 4:1 Multiplexer and 1:4 De-multiplexer using
Dataflow Modeling (Verilog).

Tools: Questasim Software (Mentor Graphics), Precision Software.

Brief theory:

4:1 Multiplexer:

A multiplexer or mux is a combinational circuits that selects several analog or digital

input signals and forwards the selected input into a single output line. A multiplexer of 2 n inputs
has n selected lines, which are used to select which input line to send to the output.
In 4:1 mux, at any one instant in time only ONE of the four analog switches is closed,
connecting only one of the input lines I0 to I3 to the single output Y. Here which switch is closed
depends upon the addressing input code on lines S0 and S1. For example, to connect input I1
to the output Y, the binary input address would need to be S0 = logic 1 and S1 = logic 0.
Figure below shows the block schematic of 4:1 mux:
 Y

Expressions for 4:1 mux:

If S1=0 and S0=0 then Y = I0

If S1=0 and S0=1, then Y = I1

If S1=1 and S0=0, then Y = I2

If S1=1 and S0=1, then Y = I3

The final Boolean expression of this multiplexer is given as:

Y= I0 S1bar S0bar+ I1 S1bar S0+ I2 S1 S0bar+ I3 S1 S0

The truth table for 4:1 mux is as shown below:

Select Line Inputs Output

S1 S0 Y

0 0 I0

0 1 I1

1 O I2

1 1 I3
 1:4 Demultiplexer:
A demultiplexer, sometimes abbreviated demux, is a circuit that has one input and more than
one output. It is used when a circuit wishes to send a signal to one of many devices. This
description sounds similar to the description given for a decoder, but a decoder is used to select
among many devices while a demultiplexer is used to send a signal among many devices.
In1:4 Demux, at any one instance, one signal can be send on any of four devices available
since it has one input which can be diverted over four outputs which are further used to drive
four devices.
The block schematic of 1:4 Demux is as shown below:

Expressions for 1:4 Demux:

If S1=0 and S0=0 then Din = Y0

If S1=0 and S0=1, then Din = Y1

If S1=1 and S0=0, then Din = Y2

If S1=1 and S0=1, then Din = Y3

The final Boolean expression of this multiplexer is given as:

Din= Y0 S1barS0bar
Din= Y1S1bar S0

Din=Y2S1S0bar

Din=Y3S1S0

The truth table for 1:4 Demux is as shown below:

Data Input Select Line Inputs Outputs

Din S1 S0 Y1 Y1 Y1 Y1
Din 0 0 0 0 0 Din
Din 0 1 0 0 Din 0
Din 1 0 0 Din 0 0
Din 1 1 Din 0 0 0

Procedure:

A. Synthesis:
1. Right click on the desktop, select the open terminal option, new window wil
appear.
2. Type csh then press enter.
3. Type imstat. It is used to check whether system is connected or not.
4. Type Vsim and enter.
5. New window will appear, open the file and then create the new project.
6. Give the name to the project.
7. Then add item to the project.
8. Create a new file, the name of file should be same as module name.
9. Add file type Verilog
10. Double click on file name.
11. Define your program in the new window appeared.
12. Compile the program to check whether it will work or not.

B. Simulation:
1. Right click on the desktop, select the open terminal option, new window will be
appear.
2. Type csh then press enter.
3. Type precision then press enter.
4. Precision window will open then click on add input files.
5. Add the hex file that you want to synthesize.
6. Click on compile button.
 7. After successful compilation, click on Synthesize.
8. Force binary values to all input signals & add waveforms to output signals.
9. The output window will appear with different reports in drop down box.
10. Check the RTL schematic.
11. Open the Area Report to check the usage done by the program.

Code:

4:1 Multiplexer:

module mux(s1, s0, i3, i2, i1, i0, y);

input i3, i2, i1, i0, s1, s0;
output y;
wire p, q, r, s, l, m;
assign l=~s1;
assign m=~s0;
assign p=l&m&i0;
assign q=l&s0&i1;
assign r=s1&m&i2;
assign s=s1&s0&i3;
assign y=p|q|r|s;
endmodule

1:4 Demultiplexer:
module demux(i,s1,s0,y0,y1,y2,y3);
input i,s1,s0;
output y0,y1,y2,y3;
wire l, m;
assign l=~s1;
assign m=~s0;
assign y0=l&m&i;
 assign y1=l&s0&i;
assign y2=s1&m&i;
assign y3=1&s0&i;
endmodule

Waveform:

4:1 Multiplexer:
 1:4 Demultiplexer:

RTL Schematic:

4:1 Multiplexer:
 1:4 Demultiplexer:

Area Report:

4:1 Multiplexer:
***************************************************************
Device Utilization for 3S100EVQ100
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 7 66 10.61%
Global Buffers 0 24 0.00%
LUTs 2 1920 0.10%
CLB Slices 1 960 0.10%
Dffs or Latches 0 2052 0.00%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%
---------------------------------------------------------------
*********************************************
Library: work Cell: mux View: INTERFACE
*********************************************
Cell Library References Total Area
IBUF xis3e 6x
LUT3 xis3e 2x 1 2 LUTs
MUXF5 xis3e 1x 1 1 MUXF5
OBUF xis3e 1x

Number of ports : 7
Number of nets : 16
Number of instances : 10
Number of references to this view : 0

Total accumulated area :

Number of LUTs : 2
Number of MUXF5 : 1
Number of gates : 2
Number of accumulated instances : 10
*****************************
IO Register Mapping Report
*****************************
Design: work.mux.INTERFACE
+-------+-----------+----------+----------+----------+
| Port | Direction | INFF | OUTFF | TRIFF |
+-------+-----------+----------+----------+----------+
| s1 | Input | | | |
+-------+-----------+----------+----------+----------+
| s0 | Input | | | |
+-------+-----------+----------+----------+----------+
| i3 | Input | | | |
+-------+-----------+----------+----------+----------+
| i2 | Input | | | |
+-------+-----------+----------+----------+----------+
| i1 | Input | | | |
+-------+-----------+----------+----------+----------+
| i0 | Input | | | |
+-------+-----------+----------+----------+----------+
|y | Output | | | |
+-------+-----------+----------+----------+----------+
Total registers mapped: 0

Total accumulated area :

Number of LUTs : 2
Number of gates : 2
Number of accumulated instances : 7
*****************************
IO Register Mapping Report
*****************************
Design: work.fulladder01.INTERFACE
+--------+-----------+----------+----------+----------+
| Port | Direction | INFF | OUTFF | TRIFF |
+--------+-----------+----------+----------+----------+
|A | Input | | | |
+--------+-----------+----------+----------+----------+
|B | Input | | | |
+--------+-----------+----------+----------+----------+
| Cin | Input | | | |
+--------+-----------+----------+----------+----------+
|S | Output | | | |
+--------+-----------+----------+----------+----------+
| Co | Output | | | |
+--------+-----------+----------+----------+----------+
Total registers mapped: 0

1:4 Demultiplexer:
***************************************************************
Device Utilization for 3S100EVQ100
***************************************************************
Resource Used Avail Utilization
---------------------------------------------------------------
IOs 7 66 10.61%
Global Buffers 0 24 0.00%
LUTs 4 1920 0.21%
CLB Slices 2 960 0.21%
Dffs or Latches 0 2052 0.00%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%
---------------------------------------------------------------
***********************************************
Library: work Cell: demux View: INTERFACE
***********************************************
Cell Library References Total Area

IBUF xis3e 3x
LUT2 xis3e 1x 1 1 LUTs
LUT3 xis3e 3x 1 3 LUTs
OBUF xis3e 4x

Number of ports : 7
Number of nets : 14
Number of instances : 11
Number of references to this view : 0

Total accumulated area :

Number of LUTs : 4
Number of gates : 4
Number of accumulated instances : 11
*****************************
IO Register Mapping Report
*****************************
Design: work.demux.INTERFACE
+-------+-----------+----------+----------+----------+
| Port | Direction | INFF | OUTFF | TRIFF |
+-------+-----------+----------+----------+----------+
|i | Input | | | |
+-------+-----------+----------+----------+----------+
| s1 | Input | | | |
+-------+-----------+----------+----------+----------+
| s0 | Input | | | |
+-------+-----------+----------+----------+----------+
| y0 | Output | | | |
+-------+-----------+----------+----------+----------+
| y1 | Output | | | |
+-------+-----------+----------+----------+----------+
| y2 | Output | | | |
+-------+-----------+----------+----------+----------+
| y3 | Output | | | |
+-------+-----------+----------+----------+----------+
Total registers mapped: 0

Conclusion:
This experiment is to verify the working of one-to-many and many-to-one data routing
systems viz. multiplexer and de-multiplexer respectively. While writing a dataflow modeling
code, we used one new keyword wire is used to define intermediate connections of gates like
inversion.
The waveforms thus obtained clearly show the working of multiplexer and de-
multiplexer. For e.g. when s1=0 and s0=1, we got output y=current status of i1. For de-
multiplexer, when s1=0 and s0=1, the data input gets routed to output 2, i.e. y2=din. Further RTL
schematic shows the internal circuitry of both of the combinational circuits. Area report
emphasizes on the device utilization done by mux as well as de-mux.