Functions and Procedures

Dr DC Hendry

May 8, 2006

1 Functions and Procedures

VHDL supports both functions and procedures. These constructs are not how-
ever used in the manner that functions are used in a language such as C. In the C
language functions are used to divide code into manageable sized units, to make
the code more efficient to write and to maintain. In VHDL this task is largely
fullfilled by the use of a design hierarchy built with components instantiated
within a larger design.

Functions and procedures have a much smaller role to play in VHDL. It is

true that many designs can be completed without any overt use of functions
and procedures, although since functions are essential for providing overloaded
operators and so for example the functionality that accompanies types signed
and unsigned, functions are implicitly used.

A function is a subprogram that returns a value. The function defines how

the return value is to be computed using a sequential algorithm. The formal
parameters of the function may be used within the algorithm.

2 Subprogram Syntax

Procedure Syntax

procedure <procedure_name> ( <formal_parameter_list> ) is

<list of subprogram declarations>

 Functions and Procedures

begin

<list of sequential statements>

end procedure <procedure_name>;

Simple Procedure Example

procedure printsumxy
(constant x : in integer;
constant y : in integer) is

variable xplusy : integer;

variable l : line;

begin

xplusy := x + y;
write(l, Sum of x and y is );
write(l, xplusy, right, 5);
writeline(output, l);

end procedure printsumxy;

Interface Elements (Formal Parameters)

The declaration of a formal parameter includes up to five items of information,

collectively known as an Interface Element. The syntax is:

[<interface class>] <parameter name> : [<mode>] <type> [:= <initial value>]

For example:

constant x : in std logic vector;

constant y : in integer := 0;
variable z : out std logic vector;

Interface Classes

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 Functions and Procedures

Each formal parameter has an interface class that is declared as part of the
formal parameters. For VHDL 93 there are four interface classes:

constant This is the default class for parameters of mode in. The actual
parameter may be a literal, a constant, a signal, a variable or an expression.
variable This is the default class for parameters of mode out. The actual
parameter must be a variable.
signal The actual parameter must be a signal.
file Only available with VHDL-93, the actual parameter must also be a file. In
VHDL-87, files are passed as parameters of class variable.

Interface Element Mode

The mode of an interface element is one of:

in The parameter is an input, and so read only. Only parameters of mode in

can include an initialisation expression.
out The parameter is an output, and so may only be written to.
inout The parameter may be both read from and written to.

Function Syntax

The syntax for a function in VHDL is:

[pure | impure] function <function_name>

( <formal_parameters> )
return <type> is

<subprogram_declarations>

begin

<sequential_statements>

end function <function_name>;

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 Functions and Procedures

Functions

1. A pure function is one that for the same input arguments, returns the
same output. A function that returns the square of an input integer is
such a function.
2. Formal parameters of functions can onlybe constant of mode in.
3. An impure function is one that may return different data for the same
data input. The supplied function now that returns the current simulation
time is such a function.
4. The function declaration must give the type of the value to be returned.
5. The value to be returned is given in a return statement within the se-
quential statements. The type of the expression in the return statement
must match the type given in the function declaration.

3 Examples

A Boolean Function: Majority Function

pure function majority

(a : std logic;
b : std logic;
c : std logic) return std logic is
begin
return (a and b) or (a and c) or (b and c);
end function majority;

This function can be called in either a sequential or a concurrent statement:

y <= majority(x1, x2, x3);

ceillog2

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 Functions and Procedures

function ceillog2 (constant n : natural)

return natural is
begin ceillog2
pragma synthesis off
assert n >= 1
report "Ceillog2: value of n is less than 1"
severity error;
pragma synthesis on
for m in 0 to 35 loop
if 2**m >= n then
return m;
end if ;
end loop;
pragma synthesis off
report "Ceillog2: value of n is too large"
severity error;
pragma synthesis on
end ceillog2;

Procedure Declarations:

The next three are taken from std logic textio.

procedure READ(L:inout LINE; VALUE:out STD LOGIC VECTOR);

procedure READ(L:inout LINE; VALUE:out STD LOGIC VECTOR;
GOOD:out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD LOGIC VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);

For the last procedure the final two formal parameters have default values, so
we may write:

WRITE(Lin, invec);

and the final two parameters assume values of RIGHT and 0 respectively.

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