Embedded Image Grabber and Processing

System Based on Camera Link

Li, Jianrong1,2; Gao, Huibin1; Wang, Zhiqian1; Geng, Tianwen1; Zhao,Yan1
1.Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences
Changchun, China
2.Graduate School of the Chinese Academy of Sciences
Beijing, China
e-mail: lijianrong_1997@sohu.com

Abstract—In order to realize real-time measurement based
on image, proposes a design project of embedded image
grabber and processing system based on camera link
interface. The system adopts FPGA+DSP structure design.
DSP used to process the image and send out processing
results to external. FPGA adopts modularize design. It
contains camera link interface module, image memory
module, DSP connection module and so on. The experiment
results show that the system design flexibility, small cubage,
high real-time image processing, and can fulfil the
requirement of real-time measurement.
Keywords- camera link interface; real-time image
processing; dsp;fpga
I. INTRODUCTION
Along with the development of image sensor, measure
technology based on image is more application. Because
the data of image is so large, so the transmission
technology, memory technology and processing
technology of image are bottle-necks of image
measurement.
Many camera and frame grabber manufacturers
contributed to the development and definition of the
camera Link standard. Camera link is a communication
interface for vision applications[1]. The interface extends
the base technology of channel link to provide a
specification more useful for vision applications.
Increasingly diverse cameras and advanced signal and
data transmissions have made a connectivity standard like
camera link a necessity[2-3]. The camera link interface will
reduce support time, as well as the cost of that support.
The standard cable will be able to handle the increased
signal speeds, and the cable assembly will allow
customers to reduce their costs through volume pricing[4-5].
This article introduces a embedded image grabber and
processing system based on camera link interface[6]. The
system adopts FPGA+DSP structure design. it can satisfy
the needs of image processing speed, also convenient
design interface with other systems.
II. SYSTEM CONFIGURATION
DSP and FPGA are the core parts of embedded image
acquisition, and processing system, and camera link
interface chip, FLASH, SRAM and so on are the periphery
parts of embedded image acquisition and processing
system. The system configuration shows as figure 1.
The principle of embedded image acquisition and
processing system as follows: First, DSP sends image
acquisition command to camera link interface module of
FPGA[7], camera link interface module configures the
camera and send external trigger to camera by CC1 control
port. Second, camera link interface module grab valid
image by DVAL signal, LVAL signal and FVAL signal of the
camera, and the same time write the data to SRAM. After store
this frame image, FPGA sends external interrupt signal to
DSP. Finally, DSP reads the data from SRAM and
processes the data, and attains measurement result. When

Figure 1. system configuration.

finish debug program of DSP, stores the program codes to
FLASH, and the same time sets the DSP work mode as
computer mode. When the system restarts work, DSP will
run the program of FLASH, and accomplish image grab
and image process.
III. DSP PROGRAM DESIGN
DSP is this image grabber and processing system
CPU, is the core of the system components. It controls the
work flow of the system, and processing image data
according to the image processing algorithm of this
system. Finally, gets the expectation calculating results
through the calculation of it, and send the calculating
results to superordination machine through the
communication interface. According to the function of
digital signal processor (DSP), DSP software mainly
includes the main program, DSP initial program, and the
upper machine subgroups of communication procedure,
image processing procedure, solving quantum procedures,
etc. For One image processing the subroutine and
contains the image extraction procedure, image judgment
subroutine, image segmentation procedure, etc. Program
flow chart shows as figure 2.
Figure 2. program flow chart.
The program flow chart shows that the main
difficulties of the program is the image processing.
Because the images is a very large amount of data,
different algorithm can make the calculation amount of
DSP has the very big difference. But in embedded
systems, data processing speed is the key, so different
image algorithm will directly influence the performance
of the system.
IV. FPGA PROGRAM DESIGN
The FPGA program uses modular design. The
program basically has camlink interface module, the
SRAM interface module, and DSP interface module, etc.
Camlink interface is a kind of camera standard
interface, and it is the most widely used camera interface
today. The embedded image grabber and processing
system can configurate the camera through the Camlink
interface, control the camera's imaging range through the
Camlink interface, control the camera unit exposure time
through the Camlink interface, control the camera's data
output format through the Camlink interface etc. And at
the same time through Camlink interface the system can
receive the output data synchronization of the camera,
receives the grey of images information, to receive the
data of image state information, etc. According to the
information, can finally obtained the camera image
information.
The earliest use of FPGA do Camlink interface is
directly in the Camlink interface LVDS signal access.
When read signals in FPGA, the first use the resources of
FPGA receives LVDS signal converted into TTL signal,
and then put these TTL signal to the assigned address
through timing read command. When sending orders, at
the first send the TTL instructions, and then convert the
TTL signals into LVDS signal. Because Camlink
interface fast data transmission, so the program is very
complex in FPGA. In order to solve this problem, the chip
manufacturers make the dedicated Camlink interface chip.
The Interface chip used as to realize interaction
conversion between the LVDS signal and TTL signal.
In this embedded image grabber and processing
system, Camera link interface chip choose ds90lv047 and
ds90cr286.
The DS90CR286 receiver converts the LVDS data
streams back into 28 bits of LVCMOS/LVTTL data. At a
transmit clock frequency of 66 MHz, 28 bits of TTL data
are transmitted at a rate of 462 Mbps per LVDS data
channel. Using a 66 MHz clock, the data throughput is
1.848 Gbit/s (231 Mbytes/s).
58 conductors are required. With the Channel Link
chipset as few as 11 conductors (4 data pairs, 1 clock pair
and a minimum of one ground) are needed. This provides
a 80% reduction in required cable width, which provides a
system cost savings, reduces connector physical size and
cost, and reduces shielding requirements due to the
cables’ smaller form factor.
The DS90LV047A is a quad CMOS flow-through
differential line driver designed for applications requiring
ultra low power dissipation and high data rates. The
device is designed to support data rates in excess of 400
Mbps (200 MHz) utilizing Low Voltage Differential
Signaling (LVDS) technology. The DS90LV047A accepts
low voltage TTL/CMOS input levels and translates them
to low voltage (350 mV) differential output signals. In
addition, the driver supports a TRI-STATE function that
may be used to disable the output stage, disabling the load
current, and thus dropping the device to an ultra low idle
power state of 13 mW typical. The DS90LV047A has a
flow-through pin out for easy PCB layout. The EN and
EN* inputs are together and control the TRI-STATE
outputs. The enables are common to all four drivers. The
DS90LV047A and companion line receiver
(DS90LV048A) provide a new alternative to high power
psuedo-ECL devices for high speed point-to-point
interface applications.
Design a control module matches with the ds90lv047
in FPGA by VHDL, for controls CC1, CC2, CC3, CC4
output. Sets application parameters to the camera and
control the external trigger of camera. The control module
shows as figure 3. The CS signal is the module control
signal. When CS signal is HIGH, the control module does
not work, output signal is not changed with input signal.
When CS signal is LOW, the module in the work, output
signal is changed with input signal. Because the control
module is very easy, so does not introduce its timing
simulation.
Figure 3. ds90lv047 control module.
Design a control module matches with the ds90cr286
in the FPGA, for receiving the image information and
clock information of camera. The control module shows
as figure 4.
Figure 4. ds90cr286 control module.
The camera output data be converted 28 parallel data
by ds90cr286 chip. Including 24 bits image data, can
teleport from 8 bits to 24 bits RGB signal image data.
This design chooses single channel black and white
output, so the data bus selects 16 bits, can satisfy the
requirements image grey adjustment. Another three bits
respectively be defined for data effective (DVAL) signal,
line effective (LVAL) signal and frame effective (FVAL)
signal, and last bit reserved. If the sender as long as the
timing driving in accordance with the contract, then the
receiver can calculate complete image information of
receive data by the three state signals[8].
When FVAL and LVAL both HIGH, the data
information is one pixel gray information in a
CAM_CLOCK clock cycle. The control module generates
write memory address and write control signal by
CAM_CLOCK signal, FVAL signal and LVAL signal.
The control module’s timing simulation figure as shown
in figure 5.
Figure 5. ds90cr286 control module timong simulation.
Design a DSP and SRAM interface module, used to
write the 16 data of image information to SRAM, also it
is used to DSP writes and reads the SRAM. The DSP and
SRAM interface module show as figure 6.
Figure 6. DSP and SRAM interface module.
DSP sends a control signal to the DSP and SRAM
interface module. The signal controls the DSP read and
write control signal to SRAM is valid or the ds90cr286
control module read and write control signal to SRAM is
valid. When receiving the camera’s data, the ds90cr286
control module controls SRAM. When processing the
image information, DSP controls SRAM.
V. CONCLUSION
This article proposed a kind of embedded image
grabber and processing system based on camera link
interface, the system adopts FPGA+DSP structure design.
It can satisfy the needs of image processing speed, also
convenient design interface with other systems. The
system contains display module, it can real-time display
measured results. The system still has superordination
machine communication serial interface, it can real-time
transmit results to superordination machine. So this
system can be applied to protection monitoring and image
measurement, etc.
ACKNOWLEDGMENT
This work was supported in part by the jilin Provincial
Science &Technology department. The authors gratefully
acknoledge the funding of this study by nature science
research project (Grand NO. 201115124).
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