Department of Computer Engineering

CSE 323
Computer Organization
S P R I N G ‘ 0 4
XILINX TUTORIAL

• A NEW PROJECT

Click on the icon on the desktop or Xilinx Foundation tools or go to the window's START
menu -> Programs -> Xilinx Foundation Series -> Xilinx Foundation Project Manager.

Select Create New Project and Ok. Enter a new project name, set the directory for your
project as desired. Under Flow, select Schematic. The three pulldown boxes at the bottom of
the New Project window refer to the device family, the part and the speed grade.
The Project Manager window will open as below.

Click on the Schematic Editor box (shown below) in the Project Manager. The Schematic
Editor window should appear with a blank schematic. You can also open the Schematic
Editor by selecting Tools/Design Entry/Schematic Editor from the menus.
• SCHEMATIC EDITOR

To add digital logic to the schematic, select the SC SymbolsToolbox from the schematic
editor toolbar on the left side of the schematic editor window using the button shown below.

The SC SymbolsToolbox should appear as shown below.

Select and drag the part you need.

As an example let’s build a two input AND gate.

Select AND2 part from the SC Symbols Toolbox and drag it on the editor. To be able to give
input to the part select Hierarchy Connector from the schematic editor toolbar on the left
side of the schematic editor window using the button shown below.

A menu will appear allowing you to enter the name of the terminal and type of it.

Click the OK button to close the dialog. The mouse pointer will adopt a new shape ( ).
Move the mouse pointer over the desired location and click the mouse button to place the
terminal symbol.

Hint: If you want to place several terminal symbol whose name consist of a fixed prefix and
consecutive numbers, click the Repeat button instead of OK. After having placed the first
terminal, for example, A3, successive clicks will place consecutive terminals A4, A5, A6, and
so on. To leave the repeating mode, press the Esc key.

To draw wires, switch to the Draw Wires mode. In this mode the mouse looks as shown
below:

To switch to the Draw Wires mode, choose Draw Wires from the Mode menu or click the
Draw Wires button in the Schematic toolbar.

To start a wire, click a pin or terminal or existing wire. When you move the mouse
pointer now, a temporal wire line will be stretched between its origin and the current
location of the mouse pointer. If the Orthogonal mode is enabled, the wire line will
automatically bend at right angles. To anchor a corner, click the mouse button. The
fixed segment of the wire will turn blue.

You can cancel the connection at any moment by pressing the Esc key.
To complete the connection, move the mouse pointer over another pin, terminal or
wire, and then click the mouse button.

The figure below represents the work we have done so far.

Or you can place a power symbol as an input, select Power Symbol from the schematic
editor toolbar on the left side of the schematic editor window using the button shown below.

A dialog box will appear:

From the PWR Signal Type list box select the desired power new type. In boxes PWR Name
and PWR Shape, default power net name and symbol shape will appear. Click OK to close
the dialog. Move the mouse pointer over the desired location and click the mouse button to
place the power symbol.

Hint: If you want to place several power symbols, click the Repeat button instead of OK.
Consecutive clicks will place multiple power symbols. To leave the repeating mode, press the
Esc key.

Or you can give inputs using IPAD’s and IBUF’s in the SC Symbols Toolbox. Label the
wires between IPAD and IBUF, and OBUF and OPAD by double click on the wire. A
window will appear. Enter the name of the wire such as IN1, IN2, or OUT. These labels are
used to set the nodes to be analyzed during simulation.

• NETLIST AND INTEGRITY TEST

You will need to generate a netlist which is in a format that is readable by the compiler. This
is done by going to the OPTIONS menu-> CREATE NETLIST. When finished, it is always a
good idea to check that the schematic has no electrical design rule errors. This is done from
the OPTIONS menu -> INTEGRITY TEST.
• FUNCTIONAL SIMULATION

In the Project Manager window, select Simulation (functional simulation) by clicking on

the large button shown below. The Simulator can also be opened from the Schematic Editor
by clicking on the simulation icon shown below.

Waveform viewer will appear as shown below:

Signals must be added to the Waveform Viewer so they can be simulated. In the Signal
menu, select Add Signals. Figure below shows the window that you will get. All the signals
and probes will be presented in this window. Select the important signals to view by holding
down Ctrl and then Clicking on each signal that you wish to add, then Click Add. Click on
Close. The Waveform Viewer window should now list the signals you chose.
You must now apply stimulus to the input signals. In the Signal menu, select Add
Stimulators. The Stimulator Selection window will now appear with a keyboard, clocks,
and counters.

The Keyboard section lists all keyboard keys that can be assigned to signals and used as
design stimulators. Each stimulator key works as a toggle switch that is switching between
logical 0 and 1 every time the appropriate keyboard key is pressed. The keys 0 and 1 are used
to assign constant logical 0 and 1 stimuli signals, respectively.

The Clocks section allows assigning clock stimulators defined in the Set Formula window.
Clock stimulators are marked C1, C2, C3 and C4.

If the CS (Custom select) stimulator is assigned to an existing waveform, this waveform will
be forced into the design as the driving signal during simulation.

The Bc section (row of Light Emitting Diodes) represents outputs of a software-driven 16-bit
binary counter. These bits can be assigned as design stimuli to unlimited number of signals
and input or output pins. The clock frequency of this binary counter is set from Binary
Counter Settings window. The Simulation tab of the Preferences tab of Options window
allows:
o selection of the period/frequency of the bit 0 of the software-driven 16-bit binary
counter. Select either the B0 period or B0 frequency from the drop-down lists. The
other corresponding parameter will be automatically adjusted. You can also type new
values directly into boxes.
o selection of the simulation precision. Select desired value from the Simulation
Precision box. Please note that the simulation precision is different from the
simulation step!
o setting the number of memory words that will be simulated (Memory Range)
o selecting transport delay mode for line delays.
The NBc section (row of Light Emitting Diodes) represents inverted outputs of the software-
driven 16-bit binary counter, which can be used as the design stimuli signals. The clock
frequency of this binary counter is set from the Binary Counter Settings window.

The Form section is comprised of 16 square lights, which represent the associated user
defined signal waveforms, also called the Formula Stimulators. The Formula Stimulators can
be defined in the Set Formula window.

The Delete button removes stimulator from the selected signal.

The EN button enables the previously disabled stimulator.

The DS button disables the selected stimulator.

The CC button switches stimulator to the Chip Controlled mode, in which the stimulator will
produce a weak signal that may be overridden by device or cell strong output.
The OV button switches the selected stimulator to Override mode (the stimulator will produce
a signal stronger than produced by any circuit output).

You are now ready to simulate your design. In the small Simulator window select the
simulation step button shown below:

Waveforms should now appear that correspond to each signal that is being viewed.

(6) Step the simulation forward a few steps and observe the waveforms. You may want to use
the Zoom In and Zoom Out buttons shown below to manipulate the simulation display
window:

Following figure shows the results of simulation.

 • BUSES
A bus is merely a grouping of individual signals.
Buses are used to add clarity to a schematic drawing and also for convenience. It would not
be very fun to draw and label every wire individually for a 128-bit bus!
Often a bus is a set of signals that will represent a numeric value.

Typically in the foundation tools, buses are specified in the following way.

Name[msb:lsb]

For example SUM[7:0] would be an eight bit bus named SUM. The ‘most significant bit’ of
this bus would be the signal SUM7 and the ‘least significant bit’ would be SUM0

The following illustration shows a bus and all of the signals broken out from that bus.

The bus is represented by the thick line on the screen. To draw a bus select the “Draw Buses”
button on the toolbar.
When you double click to end a bus the following window will pop-up.

In the “Name” field, type the bus name.

In the “Range” fields you can specify the MSB and LSB values of your bus (either type the
value directly or use the up/down arrows to choose a value).

Under “Terminal Marker”, you can specify the hierarchical port type…

NONE – places no port connector on the bus. Use this if the bus does not need to traverse a
level of hierarchy. Only a label will be placed next to the bus.

INPUT – places an input port connector and label on the bus

OUTPUT – places an output port connector and label on the bus

BDIRECTIONAL – places an bidirectional port connector and label on the bus

You can also choose “Bus End” to terminate a bus with no port connector and no label

SUM[7:0] – Indicates the range of the bus is 8-bits

SUM 0 - Indicates the LSB bit of 8-bit SUM input
|
|

SUM 7 - Indicates the MSB bit of 8-bit SUM input

To connect a wire to a bus, either use the “Draw Wires” tool and any wire that you draw that
ends on a bus line will automatically be connected, or use the “Bus Taps” tool. This tool can
be used to draw bus taps and wired from a symbol pin to a vertically drawn bus line.

To use the bus tap tool, Click the bus tap button ( ). Next click the bus that you wish to
connect to. Then click on the symbol pin. A wire will then be drawn from the symbol pin to
the bus. The wire will also be automatically labeled starting with the MSB.
Remember to label any wire that is connected to a bus. Since a bus is a collection of wires,
the tools have no way to know which wire you want unless you label it.
An important thing to keep in mind, is that all bus segments should be labeled. This is
necessary so that the schematic tools can determine which signals are present on any given
bus segment.

Here is an example of generating a bus from several different sources….

The BUF symbol is used to change the name of a wire. In the example above, one wire is
changed from the name INSIGNAL to RESULT15. Another wire is changed from the name
GND to RESULT12. In the Xilinx tools, the BUF does not introduce delay, its main purpose
is labeling convenience.

Finally, when choosing a bus name, do not choose a name that ends with a numeric character.

• BUSES AND SIMULATION

When simulating, buses are selected and viewed just like any other signal. However, there
are a few special things you can do that you should be aware of

Display
When looking at a bus in the simulation display, the default is to display the value of the bus
as a hexadecimal number. Here we see a simulation of the circuit drawn earlier to generate
the RESULT[15:0] bus.

If you are not happy with a hexadecimal display, then you can choose your radix. To do this,
first highlight the bus then go to the menu bar and click “Signal – Bus --- …
Display Binary
Display Octal
Display Decimal
Display Hexadecimal

If you wish to display the individual bits of the bus or place “Stimulators” on individual
signals then first you must “flatten” the bus. Flattening a bus changes the display so that
every individual bus line is visible. To do this highlight the bus then goes to the menu bar and
click “Signal – Bus --- Flatten”. Refer to the above screenshot.

• MEMORY DESIGN

Exit all Xilinx programs. Then, click "Start->Programs->Xilinx...->Accessories-

>LogiBLOX". (This should launch LogiBLOX.) Then, select a Vendor, your project
directory, and a Device Family (e.g., spartanxl) and click OK. Next, select the module type to
be "MEMORIES". Once you have done this, you will see choices for ROM, SYNC_RAM or
DP_RAM (which means dual-ported RAM). You will be using ROM for the instruction
memory and SYNC_RAM for the data memory.

Next select your "MemoryDepth" and "Data Bus Width". For memory depth, most of you will
choose 128 or 256, while the Data Bus Width must be "8". Note that the memory depth must
be a multiple of 16.

Now the part that you actually need this tutorial for. If you are programming your ROMs for
your program, or want to initialize memory nicely, you have to put in a file name, and click
on the "Edit" button beside the MemFile area. When you click on the edit button, it will pull
up a file which looks something like this.

;
; memfile data_mem.mem for LogiBLOX symbol data_mem
; Created on Thursday, February 17, 2000 11:21:48
;
; Header Section
RADIX 10
DEPTH 256
WIDTH 8
DEFAULT 0
;
; Data Section
; Specifies data to be stored in different addresses
; e.g., DATA 0:A, 1:0
RADIX 16
DATA
; end of LogiBLOX memfile

This is the file you must edit. First, you will notice the size of the memory depth and width.
This must be the same as you selected in your LogiBlox window. (LogiBlox automatically
does this for you, but if you change something later on in LogiBlox and then try to use this
file, it won't work unless you change the depth and width here too.)

Now notice the line that says DATA. The help gives a good example, but here is another one
as well.

(earlier lines of file untouched from default)

RADIX 16
DATA FF,
A: F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,FA,FB,FC,FD
FE,FF,A0
; end of LogiBLOX memfile

This demonstrates the basics of how you put data into memory. Right after the DATA
statement, any values you put in are assumed to start at memory location 0. In this example,
the value FF is put into location 0 (notice the RADIX 16 statement has changed us into
hexadecimal numbers.) On the next line, we specify values that will start at memory location
0A. 0A gets F0, 0B get F1, etc up through memory location 1A getting A0.

Be sure and save this file, in case you have errors, need to debug your programs, etc.

This type of memory file works for both ROMs and RAMs, and is the easiest way to do your
memories.

After closing LogiBLOX, you can open the Xilinx Schematic Editor again. Then, choose the
Tools option and click Import LogiBLOX. You should see a mem file that can be added.
Xilinx should create a macro for it automatically.

REFERENCES
1) Wright State University, CEG 360/350 Digital System Design, Xilinx Bus Tutorial
2) http://toolbox.xilinx.com/docsan/2_1i/
3) http://www.seas.upenn.edu/ese/rca/software/xilinx/foundation99/foundation.sch1.html