OPTIMAL WIRING TOPOLOGY FOR

ELECTROMIGRATION AVOIDANCE
CONSIDERING MULTIPLE LAYERS
AND OBSTACLES

IRIS HUI-RU JIANG

HUA-YU CHANG
CHIH-LONG CHANG

IRIS Lab National Chiao Tung University

 Outline
2 IRIS H.-R. JIANG

Introduction to EM

Problem & properties

Our approach

Experimental results

Conclusion

WiT - ISPD'2010
 Electromigration
3 IRIS H.-R. JIANG

 Electromigration (EM)
 An extremely dense electron flow (electron wind) knocks off
atoms within the wire and moves them away
 This transport leaves a gap at one end and increase the stress at
the other
 Possible failures: open-circuit / short-circuit
E
electrical field e-
electron wind

FE FP
Cu+

FE << FP

Cu+

void hillock
open short

WiT - ISPD'2010 SANYO Semiconductor Co., Ltd.

 Electromigration Is a Reliability Issue
4 IRIS H.-R. JIANG

 EM is a wear-out failure
 Triggered after being used for a period of time
 Measured in terms of mean time to failure (MTTF)
 Black’s equation, TED-1969
 Current density and working temperature
 Worsened for advanced technology nodes
 Signal nets / power network in analogEM/ mixed-signal
breakdown designs

Technology file gives the upper

bound of safe current density Jmax
under a working temperature

high current densities

WiT - ISPD'2010 J Electron Test, 2009

 EM Reliability (1/2)
5 IRIS H.-R. JIANG

 EM simulation/analysis
 Because EM occurs only after a circuit has been used for a
period of time, the defect chips cannot be filtered out during
product testing.
 It is desired to characterize the realistic current values for each
terminal/wire and to identify the wires that are potentially
threatened by EM.
 Wiring topology for EM

WiT - ISPD'2010
 EM Reliability (2/2)
6 IRIS H.-R. JIANG

 EM analysis/estimation
 Wiring topology for EM
 A thin wire should be widened for EM safety.
 Conventional EM fixing is applied at post-layout, which may use
many routing resources and layout changes.
 If a good wiring topology considering EM is applied to a router,
we may immune EM with much fewer routing resources.
 e.g.,
 Adler & Barke, DATE-2000
 Adler et. al, DAC-2000
 Lienig & Jerke, ASPDAC-2003
 Yan & Chen, APCCAS-2008

WiT - ISPD'2010
 EM Routing
7 IRIS H.-R. JIANG

 The routing resource is measured by the total wire area.

 The wire width is determined by EM-safe current density instead
of minimum printable width.
-5 -5 -5 -5
3 2
+7 +7 5 +7 +7
source
+3 7 +3 7 +3 2 7 +3 3
1
-2 -2 -2 -2
-8 -8 -8 -8
sink 2 1
1 2 2 2
5 4 4
+9 +9 +9 +9
-4 -4 -4 -4

Assume a unit width wire can carry one-unit current (normalized to 1)

-5 -5 -5 -5
+7 5↑ +7 5↑ +7 +7 5↑
7↓ 7↓ 7↓ 5↑ 7↓
5← +3 2← +3 +3 3→ +3 2→
12↓ 8↓ 1←
7↑ 2→ -2 2↑ -2 2↑ -2 3↑ -2
-8 -8 -8 -8
2→ 2→
4↓ 9↑ 1↑ 1↑ 4↑ 5↑
7← 2→ 5← 4←
5← +9 4↓
+9 +9 +9
-4 -4 -4 -4

Minimum WL = 33 ASPDAC-2003 APCCAS-2008 Ours

Area = 182 Area = 154 Area = 144 Area = 142 (optimal)
WiT - ISPD'2010
 Our Contribution
8 IRIS H.-R. JIANG

 Prior works tended towards heuristics

 State-of-the-art results
-5 -5
3
+7 5 +7
7 +3 7 +3 2

Claim: -8
-2
-8
-2
2 1
This problem1belongs to class
2 P instead of NP-hard.
2

Proof: 5
+9
4
+9
-4 -4
The greedy-choice property.
Method:
-5 -5
A strongly
+7 polynomial time
5↑ algorithm.
+7
7↓ 7↓ 5↑
+3 +3 3→
2↑ -2 2↑ -2
-8 -8
2→
1↑ 1↑ 4↑
7← 2→ 5←
5← +9 4↓ +9
-4 -4

ASPDAC-2003 APCCAS-2008
DT-based Greedy
Area = 154 Area = 144
WiT - ISPD'2010
 Outline
9 IRIS H.-R. JIANG

Introduction to EM

Problem & properties

Our approach

Experimental results

Conclusion

WiT - ISPD'2010
 Wiring Topology for EM Avoidance (TEA)
10 IRIS H.-R. JIANG

 Input
 A set S = {s1, s2, …, sm} of m current sources
 A set T = {t1, t2, …, tn} of n current sinks
 Each current source i (sink j) is associated with its flow
 The maximum tolerable current density Jmax
 The minimum feasible wire width wmin for each routing layer/via
 Output
 A wiring topology to connect all current sources and sinks in S+T
 Minimum total wire area of its detailed routing tree
 Sufficient current for each wire segment: f ∝ w
 Kirchhoff’s current conservation law
 Remarks:
 f ∝ w: The wire width offering one unit current is a layer-specific
constant.
 The current values can be DC, RMS, peak, average currents
under different EM conditions and for various signal types.
 Feasibility: ∑fsi + ∑ftj = 0
WiT - ISPD'2010
 Wirelength: Abstraction
11 IRIS H.-R. JIANG

 2D (x1, y1) p1 (x1, y1) p1

No obstacles

ly =|y1 - y2| abstraction

l(p1, p2) l(p1, p2)
= lx+ly rectilinearization

lx =|x1 - x2|
p2 (x2, y2) p2 (x2, y2)

 3D (x1, y1, z1) (x1, y1, z1)

p1 p1
With obstacles

the minimum abstraction

accumulated
area cost for rectilinearization
one unit current

p2 p2
WiT - ISPD'2010 (x2, y2, z2) (x2, y2, z2)
 Wire Area: Superposition
12 IRIS H.-R. JIANG

 Same wire area

s1 s1 s1
(xs1, ys1, fs1) fs1
fs1 fs1
fs1+fs2
t1 t1 t1
fs2
(xt1, yt1, ft1) additive
Goal: fs2
(xs2, ys2, fs2) fs2
Find
s2 the property of the optimal
s2 wiring topology. s2
⇒

The
Area may wire area estimated by the wiring topology =
vary
that at detailed
s1 routing s1 s1
(xs1, ys1, fs1) fs1 fs1
fs1
fs1+fs2
t1 t1 t1
fs1+fs2 fs1+fs2-fs1
(xt1, yt1, ft1)
= fs2
(xs2, ys2, fs2) fs1+fs2 additive
WiT - ISPD'2010 s2 s2 s2
 The Greedy-Choice Property (1/3)
13 IRIS H.-R. JIANG

 The generic form: 2 sources s1, s2 and 1 sink t1.

 fs1 + fs2 + ft1 = 0
 We prove the greedy-choice property
s1 t1

(xs1, ys1, fs1) t1 s1 (xt1, yt1, ft1)

Symmetric

s2 (xt1, yt1, ft1) (xs1, ys1, fs1) t2

(xs2, ys2, fs2) (xt2, yt2, ft2)

WiT - ISPD'2010
 The Greedy-Choice Property (2/3)
14 IRIS H.-R. JIANG

 Prove by exchange argument.

s1 s1 s1

fs1 fs2 fs1

fs1+fs2
t1 t1 t1
fs1+fs2 fs2

s2 s2 s2

A{s1 → s2 → t1} A{s2 → s1 → t1} A{s1 → t1} + A{s2 → t1}

 Axes are independent.
 Consider 3 points z1, z2 and z3 on an axis: fix z1 and z3, move z2
⇒ |z1 - z2| + |z2 - z3| ≥ |z1 - z3|
z2 z1 z2 z3 z2 Z
 A{s1 → s2 → t1} or A{s2 → s1 → t1} ≥ A{s1 → t1} + A{s2 → t1}

WiT - ISPD'2010
 The Greedy-Choice Property (3/3)
15 IRIS H.-R. JIANG

 Corollary: The greedy-choice property holds at a general multi-

layer space with obstacles.

The greedy-choice property

⇒
1. We can consider wire connections
only from sources to sinks.
2. The wire area keeps the same
after the slant edges of the greedy-
choice property are rectilinearized.

WiT - ISPD'2010
 Outline
16 IRIS H.-R. JIANG

Introduction to EM

Problem & properties

Our approach

Experimental results

Conclusion

WiT - ISPD'2010
 Overview of WiT (1/2)
17 IRIS H.-R. JIANG

+7 -5
Current sources Current sinks Layer-specific
(xsi, ysi, fsi) (xtj, ytj, ftj) Jmax, wmin
+3
WiT -2
-8
1. Length calculation

+9
2. Wiring topology generation
-4

+7 -5
3. Detailed routing

+3
Current-Correct Rectilinear Steiner tree
-8 -2

+9
-4 10
WiT - ISPD'2010
 Overview of WiT (2/2)
18 IRIS H.-R. JIANG

+7 -5
Current sources Current sinks Layer-specific (7,1)
(9, 7)
(xsi, ysi, fsi) (xtj, ytj, ftj) Jmax, wmin
(10,4)
+3
WiT -2
-8 (6, 2)
1. Length calculation (16,1)

2. Wiring topology generation (10,4) +9

-4

+7 → -5
3. Detailed routing
(8, 7) (5, 5) ↑

(2, 3) (4, 2)
(1, 8) +3 →
Current-Correct Rectilinear Steiner tree ↓
-8 ← -2
(4, 5) ↑
(5, 1) ↑
+9
-4 ← (10, 5)
WiT - ISPD'2010
 Flow Network
19 IRIS H.-R. JIANG

 Triple: (wirelength, flow, capacity)

 Feasible flow: 0 ≤ fi,j ≤ ci,j = min(|fsi|, |ftj|)

(l1,1, f1,1, c1,1) t1

s1 |ft1|
|fs1|
t2
s2 .
.
. . .
ss . .
|ftj| tt
|fsi| .
(l,i,j, fi,j, ci,j) .
tj
si
.
. . .
. . .
|fsm| . .
(lm,n, fm,n, cm,n) |ftn|
sm
tn

(0, fss, fss)

WiT - ISPD'2010
 Residual Graph
20 IRIS H.-R. JIANG

 Forward edge: push flow

 Backward edge: return flow

Flow network:
|fsi| 0 ≤ fi,j ≤ ci,j = min(|fsi|, |ftj|) |ftj|
tj
si

Residual graph:
c’i,j = ci,j - fi,j, l’i,j = +li,j
tj
si
c’i,j = -fi,j, l’i,j = -li,j

WiT - ISPD'2010
 Wire Area Optimization
21 IRIS H.-R. JIANG

 Triple: (wirelength, flow, capacity)

Flow network: t1 Residual graph: t1

flow (7,-,1)
(7,0,1) 1 1

-: undetermined

s1 (12,1,1) s1
(-12,-,-1)
3 3
(7,3,3)
3 3
5 (-7,-,-3) 5
s2 (10,2,3) s2 (10,-,1)
t2 t2
(-10,-,-2)
Area
= 7*0 + 7*3 + 12*1 +10*2
= 53
WiT - ISPD'2010
 Negative Cycle Detection (1/2)
22 IRIS H.-R. JIANG

 Theorem: Negative-Cycle Removal: If the flow assignment of a

flow network is optimal, there exists no negative cycles in its
residual graph.
Residual graph: t1
(7,-,1) 1

Push a flow along the

s1 Negative negative cycle
cycle! (-12,-,-1) ⇒
3 1. Reduce the area cost
2. Flow = min residual cap
3 (-7,-,-3) 5
s2 (10,-,1)
t2
(-10,-,-2)
7 + (-12) + 10 + (-7) = -2

WiT - ISPD'2010
 Negative Cycle Detection (2/2)
23 IRIS H.-R. JIANG

 Theorem: Negative-Cycle Removal: If the flow assignment of a

flow network is optimal, there exists no negative cycles in its
residual graph.
Residual graph: t1 Flow network: t1

(7,1,1) 1 1
(7,1,1)

s1 Negative s1
cycle! (-12,-1,-1) (12,0,1)
3 3
(-7,-1,-3) (7,2,3)
3 3
5 5
s2 (10,1,1) (10,3,3)
t2 s2
t2

Area
= 7*1 + 7*2 + 12*0 +10*3
= 51
WiT - ISPD'2010
 The WiT Algorithm
24 IRIS H.-R. JIANG

WiT(S, T)
1. construct the flow network and calculate paths and lengths
2. if the given flow at sources/sinks is legal then
3. find an initial flow assignment
4. while there exists a negative cycle in the residual graph do
5. remove the negative cycle
6. update the flow network
7. update the residual graph
8. rectilinearize the wiring topology by stored paths
 Initial solution:
 For efficiency, we select the greedy method.
 For effectiveness, we choose the minimum wirelength as the
greedy rule.

WiT - ISPD'2010
 Outline
25 IRIS H.-R. JIANG

Introduction to EM

Problem & properties

Our approach

Experimental results

Conclusion

WiT - ISPD'2010
 Results
26 IRIS H.-R. JIANG
 Implementation:
 C++ language with LEDA package
 NB with an Intel® Core™2 CPU T9400 of 2.53 GHz frequency and 4
GB memory under Windows Vista™ Business 64 bit Service Pack 1
OS.
Testcase INP1 INP2 INP3 INP4 IND1 IND2 IND3 IND4 IND5 RT01 RT02 RT03 RT04 RT05
#Terminals 7 16 10 16 10 10 10 25 33 75 180 303 475 850
Area 154 122 210 32 6,661 79,400 FAIL 23,112 31,466 FAIL FAIL FAIL FAIL FAIL
ASPDAC-2003
Runtime (s) 0.001 0.002 0.001 0.002 0.038 0.016 - 0.016 0.040 - - - - -
Area 144 98 128 40 5,319 79,000 6,181 16,000 20,814 189,437 10,638,884 3,360,716 6,475,941 59,207,240
Runtime (s) 0.001 0.002 0.001 0.002 0.001 0.001 0.001 0.003 0.005 0.120 4.958 45.553 297.806 8,573.453
Refined area 142 90 116 32 5,301 74,200 5,513 13,728 17,044 144,071 7,151,286 2,325,806 4,205,757 37,318,054
APCCAS-2008
Gain 2 8 12 8 18 4,800 668 2,272 3,770 45,366 3,487,598 1,034,910 2,270,184 21,889,186
#Iterations 1 2 1 1 1 3 15 20 29 147 622 1,938 4,288 9,238
Refine runtime (s) 0.000 0.000 0.001 0.000 0.000 0.001 0.001 0.002 0.003 0.028 0.496 4.741 28.883 440.429
Initial area 142 94 116 32 5,301 78,200 5,629 15,092 19,624 156,489 8,139,250 2,840,420 4,831,845 45,677,120
Initial runtime (s) <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 0.015 0.042 0.109 0.425
Final area 142 90 116 32 5,301 74,200 5,513 13,728 17,044 144,071 7,151,286 2,325,806 4,205,757 37,318,054
WiT
Gain 0 4 0 0 0 4,000 116 1,364 2,580 12,418 987,964 514,614 626,088 8,359,066
#Iterations 0 1 0 0 0 3 2 17 37 78 415 949 1,197 3,487
Total runtime (s) <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 <0.001 0.016 0.297 1.794 6.489 89.497

 Efficient initial solution.

 We can refine any initial solution to the optimal.

WiT - ISPD'2010
 RT05: 850 Terminals
27 IRIS H.-R. JIANG

ASPDAC-2003 APCCAS-2008 Ours

FAILED Area = 59,207,240 Area = 37,318,054

WiT - ISPD'2010
 Conclusion
28 IRIS H.-R. JIANG

 In this paper, we focus on wiring topology generation for

avoiding electromigration for power networks or signal nets in
analog and mixed-signal designs.
 The major contribution is that we claim this problem belongs to
class P instead of class NP-hard.
 Based on the proof of the greedy-choice property, we
successfully model this problem on a multi-source multi-sink
flow network and then can solve it in a strongly polynomial
time.
 Experimental results prove the efficiency and effectiveness of
our algorithm.

WiT - ISPD'2010
29 Thank You!

Iris Hui-Ru Jiang

huiru.jiang@gmail.com

WiT - ISPD'2010
30 Backup slides

WiT - ISPD'2010
 Multi-Source Multi-Sink Circuits?
31 IRIS H.-R. JIANG

 Q: What kind of design has multiple sources and sinks?

 A: Usual in analog or mixed signal designs, power network, etc.

WiT - ISPD'2010
 Non-uniform Temperature Distribution
32 IRIS H.-R. JIANG

 Q: What if non-uniform temperature distribution within a chip?

 A: This abstraction still works with given temperature
distribution map.

WiT - ISPD'2010