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22 Ant Brain
22 Ant Brain
Last lecture
Introduction to finite-state machines
Example: A sequence detector FSM
Example: A vending machine FSM
Today
A bigger example
Ant-brain FSM
CSE370, Lecture 22 1
Ant in a maze
Electronic ant, electronic maze
Design the ant
0,127
exit 127,127
start
0,0
127,0
CSE370, Lecture 22 2
Example: ant brain (Ward, MIT)
Sensors: L and R antennae, 1 if in touching wall
Actuators: F - forward step, TL/TR - turn left/right
slightly
Goal: find way out of maze
Strategy: keep the wall on the right
CSE370, Lecture 22 3
CSE370, Lecture 22 4
Example: ant brain (special case 2)
Ant Lost
CSE370, Lecture 22 5
CSE370, Lecture 22 6
Ant behavior
CSE370, Lecture 22 7
Movement:
F ≡ forward one step
TL ≡ turn left 90 degrees
TR ≡ turn right 90 degrees
CSE370, Lecture 22 8
Notes & strategy
Notes
Maze has no islands
Corridors are wider than ant
Don’t worry about startup
Assume a Moore machine
Assume D flip-flops
Strategy
Partition your design into datapath and control
Keep the wall on the right
CSE370, Lecture 22 9
exit
Reset
Done Flag
exit
CSE370, Lecture 22 10
The maze
Virtual maze
128 × 128 grid
Stored in memory
16384 8-bit words
YX is maze addresses
X is the ant’s horizontal position (7 bits)
Y is the ant’s vertical position (7 bits)
Each memory location says
00000001 ≡ No wall
00000010 ≡ North wall
Can have multiple walls
00000100 ≡ West wall
Example: 00001100
00001000 ≡ South wall
⇒ Walls on South and East
00010000 ≡ East wall
00100000 ≡ Exit
CSE370, Lecture 22 11
CSE370, Lecture 22 12
What you need
An FSM for the ant
3 outputs
Go forward
Turn left
Turn right
CSE370, Lecture 22 13
Recommendations
7-bit counters for X, Y
Move horizontally: Increment or decrement X
Move vertically: Increment or decrement Y
CSE370, Lecture 22 14
Partition the design
Forward
Ant-Brain Antennae L Maze
Turn right SRAM
FSM logic R Data
Turn left
Increment
North Decrement X counter
Heading South Preload
SRAM Address
(shift register) East Increment
West Decrement Y counter
Preload
CSE370, Lecture 22 15
CSE370, Lecture 22 16
Step 1a: State diagram
L’ R
exit
L’ R
L R
Reset
Done Flag
L exit
L’ R’
CSE370, Lecture 22 17
CSE370, Lecture 22 18
Step 2: State minimization
Two states are equivalent if they cannot be
distinguished at the outputs of the FSM
The outputs are the same for any input sequence
CSE370, Lecture 22 19
CSE370, Lecture 22 20
Step 4: Minimize the logic
X+ X Y+ X
0 1 0 0 0 0 1 0
0 0 0 0 1 1 1 0
R R
1 1 1 0 1 1 1 0
L L
1 1 1 0 1 1 1 0
Y Y
F X TL X TR X
1 1 0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 0 1 0 0 0 0 1
R R
1 1 0 0 0 0 1 0 0 0 0 1
L L L
1 1 0 0 0 0 1 0 0 0 0 1
Y Y Y
CSE370, Lecture 22 21
Ant-Brain FSM
Forward
Maze
X+ = LY+LX’+X’YR’
Turn Data L
Y+ = XY+X’R+X’L Antennae
right SRAM
F = X’ SRAM logic R
TL = XY Turn Address
TR = XY’ left
N S E W
L R
CSE370, Lecture 22 22
Antennae logic
Each memory location says Logic for right antennae
00000001 ≡ No wall R = NW(N + W) +
00000010 ≡ North wall (NW) WW(W + S) +
00000100 ≡ West wall (WW)
SW(S + E) +
00001000 ≡ South wall (SW)
00010000 ≡ East wall (EW) EW(E + N)
00100000 ≡ Exit
Logic for left antennae
The ant can be heading L = NW(N + E) +
N: 0001
W: 0010 WW(W + N) +
S: 0100 SW(S + W) +
E: 1000
Gate count:
4 2-input ORs EW(E + S)
8 2-input ANDs
2 4-input ORs
CSE370, Lecture 22 23
CSE370, Lecture 22 24
Extra Credit:
Design the memory controller:
Forward
East
West X counter
Preload SRAM Address
Forward
North
Y counter
South
Preload
Preload: load a pre-defined constant into the counters
Due last day in class, Friday, Dec. 11; printouts only
Value: up to ½ exam 1
Graded on clarity and completeness of explanation
CSE370, Lecture 22 25