start stop out2 out1

1 i1 i2 o2 o1
(OUT)
out1
o1

out1 timer1
2 o1 t1
(TIM)

timer1 stop out4 out2

3 t1 i2 o4 o2
(OUT)
out2
o2

out2 timer3 timer2

4 o2 t3 t2
(TIM)

timer2 timer3 out4 out3

5 t2 t3 o4 o3
(OUT)
out3
o3

out3 timer3
6 o3 t3
(TIM)

out3 stop counter1

7 o3 i2 c1
(CTR)

counter1 stop out4

8 c1 i2 o4
(OUT)
out4
o4

out4 counter1
9 o4 c1
[RSctr]