library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ADDER is

Port (

CIN : in STD_LOGIC;

A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

S3, S2, S1, S0: out STD_LOGIC;

COUT: out STD_LOGIC

);

end ADDER;

architecture Behavioral of ADDER is

signal Z: STD_LOGIC_VECTOR(4 downto 0);

begin

-- Z<=(A3 & A2 & A1 & A0) + (B3 & B2 & B1 & B0) + CIN;

Z<= ("0" & A) + ("0" & B) + (CIN);

S0 <= Z(0);

S1 <= Z(1);

S2 <= Z(2);

S3 <= Z(3);

COUT <= Z(4);

end Behavioral;
entity ADDER_TB is

-- Port ( );

end ADDER_TB;

architecture Behavioral of ADDER_TB is

COMPONENT ADDER

Port ( CIN : in STD_LOGIC;

A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

S3, S2, S1, S0: out STD_LOGIC;

COUT: out STD_LOGIC

);

end COMPONENT;
 --inputs

signal CIN : STD_LOGIC;

signal A : STD_LOGIC_VECTOR(3 downto 0);

signal B : STD_LOGIC_VECTOR(3 downto 0);

--outpouts

signal S3 : STD_LOGIC;

signal S2 : STD_LOGIC;

signal S1 : STD_LOGIC;

signal S0 : STD_LOGIC;

signal COUT : STD_LOGIC;

--signal :Z STD_LOGIC_VECTOR(4 downto 0);

begin

UUT:ADDER PORT MAP (CIN => CIN, A => A, B => B,

S3 => S3, S2 => S2, S1 => S1, S0 => S0, COUT => COUT);

stim_proc: process

begin

wait for 10 ns;

A <= "1010";

wait for 10 ns;

B <= "1010";

wait for 10 ns;

CIN <= "1";

wait;

end process;

end Behavioral;