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Elbert V2 V9
Elbert V2 V9
User Guide
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1 Elbert V2 Spartan 3A FPGA Development Board – User Guide
Introduction
Elbert V2 is an easy to use FPGA Development board featuring Xilinx Spartan-3A FPGA. Elbert V2 is
specially designed for experimenting and learning system design with FPGAs. This development board
features Xilinx XC3S50A TQG144 FPGA. The USB 2.0 interface provides fast and easy configuration
download to the on-board SPI flash. You don’t need a programmer or special downloader cable to
download the bit stream to the board.
Applications
• Product Prototype Development
• Home Networking
• Signal Processing
• Wired and Wireless Communications
• Educational tool for schools and universities
Board features
Components/Tools required
Along with the module, you may need the items in the list below for easy and fast installation.
Connection Diagram
This diagram should be used as a reference only. For detailed information, see Elbert V2 schematics at
the end of this documentation. Details of individual connectors are as below.
USB Interface
The on board full speed USB controller helps a PC/Linux/Mac computer to
communicate with this module. Use a USB A to Mini B cable to connect
with a PC. By default the module is powered from USB so make sure not to
overcrowd unpowered USB hubs (the picture on the left shows USB Mini
connector).
DC Power Supply
This module uses +5V power supply to function properly. By default the
board is configured to use +5V supply from USB. So an external +5V power
is not required unless USB port is unable to supply enough current. In
most cases USB ports are capable of providing enough current for the
module. Current requirement for this board largely depends on your
application. Please consult FPGA datasheet for more details on power
requirements. If for any reason, an external 5V power supply needs to be
used for the module, the Power select jumper should be configured
properly before connecting the power supply. Please refer to the marking
on the board for more details.
Power Select
The Solder jumper is used to configure the power source for the board. The Solder jumper in pin 1 and
2 is shorted to switch the power source to on board USB port and pin 2 and 3 to use the external DC
power.
JTAG Connector
JTAG connector provides access to FPGA's JTAG pins. A XILINX platform cable can be used for JTAG
programming.
VGA
The VGA interface provides this board the ability to generate VGA signals from FPGA and display
information any Display/monitor that supports standard VGA connector. This VGA interface uses
resistor network based DAC for easy use and code implementation. This 8 bit VGA interface can
display up to 256 colors.
Two IOs on the FPGA are dedicated for generating two channels of audio. Different audio tones can be
generated by using PWM and Frequency synthesis. The VGA interface provides this board the ability
to generate VGA signals from FPGA and display information any Display/monitor that supports
standard VGA connector. This VGA interface uses resistor network based DAC for easy use and code
implementation. This 8 bit VGA interface can display up to 256 colors.
Two IOs on the FPGA are dedicated for generating two channels of audio. Different audio tones can be
generated by using PWM and Frequency synthesis.
GPIOs
This board is equipped with 39 user IO pins that can be used for various custom applications. Pin
assignments on the connectors are available in the tables below.
HEADER P1
HEADER P6
9 GND NA
10 GND NA
11 VCCAUX NA
12 VCCAUX NA
HEADER P2
HEADER P4
8 IO_L09N_0/GCLK11 132
9 GND NA
10 GND NA
11 VCCAUX NA
12 VCCAUX NA
HEADER P5
Driver Installation
Windows
This product requires a driver to be installed for proper functioning when used with Windows. The
driver package can be downloaded from the product page. To install the driver, unzip the contents of
the downloaded driver package to a folder. Attach USB cable to the PC and when asked by Windows
device installation wizard, point to the
folder where driver files are present.
When driver installation is complete,
the module should appear in Windows
Device Manager as a serial port (see
the picture on the right). Note down
the name of the serial port (COM1,
COM2 etc..). This information is
required while programming the
module with configuration tool.
Linux
To use this product with Linux, USB CDC driver needs to be compiled in with the kernel. Fortunately,
most Linux distributions (Ubuntu, Redhat, Debian etc..) has this driver pre-installed. The chances of
you requiring to rebuild the kernel to include the USB CDC driver is very slim. When connected to a
Linux machine, this product should appear as a serial port in the /dev directory. Usually the name of
the device will be “ttyACMx” or similar. The name may be different depending on the Linux
distribution you have.
Mac
Similar to Linux, Mac operating system comes with the required drivers pre-installed. When connected
to a Mac computer, the device should appear as a serial port.
Step 1: Right click on the “Generate Programming File” option in “Processes” window.
Step 2: Select “Process Properties” from the pop up menu. In the dialog box, check “Create Binary
Configuration File” Check box and click “Apply”.
Step 3: Click “OK” to close the dialog box. Right click on “Generate Programming File” option again and
select “Run”. Now you will be able to find a .bin file in the project directory and that file can be used
for Elbert V2 configuration.
Powering Up Elbert V2
Elbert V2 can be powered directly from USB port so make sure that you are using a USB port that can
power the board properly. It is recommended to connect the board directly to the PC instead using a
hub. It is practically very difficult to estimate the power consumption of the board, as it depends
heavily on your design and the clock used. XILINX provides tools to estimate the power consumption.
In any case if power from USB is not enough for your application, an external supply can be applied to
the board. Elbert V2 requires two different voltages, a 3.3V and a 1.2V supply. On-board regulators
derive these voltages from the USB/Ext power supply.
Configuring Elbert V2
The Elbert V2 Spartan6 module can be configured by two methods,
Elbert V2 has an on-board micro-controller which facilitates easy reprogramming of on-board SPI flash
through USB interface. The micro-controller receives bit stream from the host application and
program it in to the SPI Flash and lets the FPGA boot from the flash. The Elbert V2 configuration
application can be downloaded from www.numato.com for free. When Elbert V2 is connected to PC, it
shows up as a COM port in Device Manager. Run configuration application, select proper COM Port
before downloading bit stream. Click on “Open File” to select the bit stream file (.bin) and press
“Program” button to download the bit stream. Wait till the download process is finished. Once the
download process is over, the configuration controller will try to boot the FPGA from the SPI Flash
automatically. Follow the below steps.
Step 1: Open Elbert V2 Configuration Tool. Select the port no.(Refer “Driver installation” for more
information on finding port no.) Click Open file and select the .bin file.
Step 2: Click on “Program” button. Wait till “Done” appears on the screen.
Step 4: Double click on “Generate File”. “Generate Succeeded” will be displayed as shown in fig below
if the mcs file is generated successfully.
Step 2: If the device is detected properly you will get a pop up window as shown below, Click OK. Then
right click on the SPI/BPI (next to the black arrow in the below fig.), select Add SPI/BPI Flash.
Step 3: Select the ".mcs" file we already created and click OK. Now choose “M25P16” in the dialogue
box appeared, then click OK.
Step 4: Click on “Flash”, Double Click on Program, select OK. If the programming is successful, a
confirmation message will be displayed.
Technical Specifications
Parameter * Value Unit
Basic Specifications
Number of GPIOs 39
Number of LEDs 8
Number of Push Buttons 6
SPI Flash Memory (M25P16) 16 Mb
Power supply voltage (USB or external) 5-7 V
FPGA Specifications
Internal supply voltage relative to GND –0.5 to 1.25 V
Auxiliary supply voltage relative to GND –0.5 to 3.75 V
Output drivers supply voltage relative to GND –0.5 to 3.75 V
* All parameters considered nominal. Numato Systems Pvt Ltd reserve the right to modify products without notice.
Physical Dimensions
Schematics
See next page.
A A
Spartan
7Seg_[0...7] 7Seg_[0...7]
7Seg_1en 7Seg_1en
MCLK MCLK
7Seg_2en 7Seg_2en
SCK SCK
7Seg_3en 7Seg_3en
CS CS
PIC SO SO
SI SI Vsync Vsync
Hsync Hsync
B[0..1] B[0...1]
G[0..2] G[0...2]
R[0..2] R[0...2]
POWER SUPPLY
Expansion Modules.sch
Spartan.sch
Power Supply.sch
D D
E E
License : CC BY-SA
http://www.numato.com
Numato Lab
File: ElbertV2.sch
Sheet: /
Title: Elbert - Spartan 3A FPGA Development Board
Size: A3 Date: 25 mar 2014 Rev:
KiCad E.D.A. Id: 1/5
1 2 3 4 5 6 7
1 2 3 4 5 6 7
SPARTAN -XC3S50A
VCCIO
VCCAUX VCCINIT
A A
119
136
108
133
122
86
95
40
61
14
23
36
66
22
52
94
TMS 1 EXPANSION CONNECTORS
VCCINT
VCCINT
VCCINT
VCCINT
VCCO0
VCCO0
VCCO1
VCCO1
VCCO2
VCCO2
VCCO3
VCCO3
VCCAUX
VCCAUX
VCCAUX
VCCAUX
TMS
TDO 107 TDO
TDI 2 TDI
TCK 109 TCK P1
IN_L13P_3 33
GPIO0 1 2 GPIO1
35
SJ1
GS2
DONE 73 IN_L13N_3/VREF_3 GPIO2 3 4 GPIO3
DONE DONE 31 GPIO0 VS2
PROGB 144 IO_L12P_3 GPIO4 5 6 GPIO5
PROGB PROG_B 32 GPIO1
SUSPEND 74 IO_L12N_3 GPIO6 7 8 GPIO7
SUSPEND 28
SJ2
GPIO2
GS2
IO_L11P_3 GND 9 10 GND
GND
IO_L11N_3 30 GPIO3 VS1
IP7 142 IO_0 VCCAUX 11 12 VCCAUX
IO_L10P_3 27 GPIO4
7Seg_2 111
SJ3
GS2
IO_L01N_0 29 GPIO5
7Seg_3 110 IO_L10N_3 VS0
IO_L01P_0 24 GPIO6 P6
7Seg_0 113 IO_L09P_3 GPIO8 1 2 GPIO9
IO_L02N_0 25
SJ4
GPIO7
GS2
7Seg_1 112 IO_L09N_3 GPIO10 3 4 GPIO11
IO_L02P_0/VREF_0 19 GPIO8 M2
7Seg_4 117 IO_L08P_3/TRDY2/LHCLK6 GPIO12 5 6 GPIO13
IO_L03N_0 21 GPIO9
7Seg_6 115 IO_L08N_3/LHCLK7 GPIO14 7 8 GPIO15
IO_L03P_0 18
SJ5
GPIO10
GS2
7Seg_5 116 IO_L07P_3/LHCLK4 GND 9 10 GND
GND
IO_L04N_0
B
7Seg_[0...7] 7Seg_7 114
121
IO_L04P_0 3 IO_L07N_3/LHCLK5
IO_L06P_3/LHCLK2
20
15
GPIO11
GPIO12
M1
VCCAUX 11 12 VCCAUX
B
SJ6
GS2
7Seg_2en IO_L05N_0 16 GPIO13
120 IO_L06N_3/IRDY2/LHCLK3 M0
7Seg_1en IO_L05P_0 12 GPIO14 P2
IP4 126 IO_L05P_3/LHCLK0 GPIO16 1 2 GPIO17
IO_L06N_0/GCLK5 13 GPIO15
7Seg_3en
IP3
IP1
124
127
125
IO_L06P_0/GCLK4
IO_L07N_0/GCLK7
0 IO_L05N_3/LHCLK1
IO_L04P_3
IO_L04N_3/VREF_3
10
11
GPIO16
GPIO17
GPIO18
GPIO20
GPIO22
3
5
7
4
6
8
GPIO19
GPIO21
GPIO23
IO_L07P_0/GCLK6 7 GPIO18
IP5 131 IO_L03P_3 GND 9 10 GND
IO_L08N_0/GCLK9 8 GPIO19
MCLK 129 IO_L03N_3 VCCAUX 11 12 VCCAUX
MCLK IO_L08P_0/GCLK8 3 GPIO20
GPIO31 132 IO_L02P_3
IO_L09N_0/GCLK11 5 GPIO21
GPIO30 130 IO_L02N_3 P4
IO_L09P_0/GCLK10 4 GPIO22 GPIO24 1 2 GPIO25
GPIO29 135 IO_L01P_3
IO_L10N_0 6 GPIO23 GPIO26 3 4 GPIO27
GPIO28 134 IO_L01N_3
IO_L10P_0 XC3S50AN/TQG144 VCCAUX GPIO28 5 6 GPIO29
GPIO27 139 IO_L11N_0 DP[1..8]
IP_2/VREF_2 53 GPIO30 7 8 GPIO31
GPIO26 138 IO_L11P_0 U1
IO_L14P_2/D1 70 DP1 GND 9 10 GND
GPIO25 143 IO_L12N_0/PUDC_B
IO_L14N_2/CCLK 72 SCK
SCK
VCCAUX 11 12 VCCAUX
GPIO24 141 IO_L12P_0/VREF_0
IO_L13P_2/D2 69 DP2
140
4.7K
4.7K
IP8
R35
R36
IP_0 71 SO
IP2 123 IO_L13N_2/D0/DIN/MISO SO
IP_0/VREF_0 67 INITB
IO_L12P_2/INIT_B INITB
68 DP3 P5
SW2 79 IO_L12N_2/D3 IP1 1 2 IP2
IO_1 63 DP5 PROGB
SW3 78 IO_L11P_2/AWAKE IP3 3 4 IP4
IO_L01N_1/LDC2 64 DP4
C SW5 76 IO_L11N_2/DOUT INITB IP5 5 6 IP6
IO_L01P_1/HDC 58 DP8 C
SW4 77 IO_L10P_2/GCLK2 IP7 7 8 IP8
IO_L02N_1/LDC0 60 DP6
SW[1..6] SW6 75 IO_L10N_2/GCLK3 GND 9 10 VCCAUX
IO_L02P_1/LDC1 57
84 IO_L09P_2/GCLK0 CLK
CMD IO_L03N_1 59 DP7
82 IO_L09N_2/GCLK1
DAT1 IO_L03P_1 54 LED2
85 IO_L08P_2/GCLK14 LED[1..8]
DAT3 IO_L04N_1/RHCLK1
DAT0
AUDIO_L
83
88
IO_L04P_1/RHCLK0
IO_L05N_1/TRDY1/RHCLK3
2 IO_L08N_2/GCLK15
IO_L07P_2/D5
55
50
51
LED1
LED4
LED3
87 IO_L07N_2/D4
AUDIO_R IO_L05P_1/RHCLK2 47 LED7
92 IO_L06P_2
Vsync IO_L06N_1/RHCLK5 49 LED5
B[0..1]
DAT2
Hsync
IP6
90
93
91
IO_L06P_1/RHCLK4
IO_L07N_1/RHCLK7
1 IO_L06N_2/D6
IO_L05P_2
IO_L05N_2/D7
46
48
LED8
LED6 JTAG
IO_L07P_1/IRDY1/RHCLK6 43 VS2
B1 98 IO_L04P_2/VS2
G[0..2] IO_L08N_1 45 VS0 P3
B0 96 IO_L04N_2/VS0 1 2 VCCAUX
IO_L08P_1 42
G1 101 IO_L03P_2/RDWR_B 3 4 TMS
IO_L09N_1 44 VS1
G0 99 IO_L03N_2/VS1 R34 D9 5 6 TCK
IO_L09P_1 39 M2 DONE 1 2 GND
R1 104 IO_L02P_2/M2 1.5K 7 8 TDO
IO_L10N_1 41 CS
G2 102 IO_L02N_2/CSO_B CS 9 10 TDI
IO_L10P_1 37 M1 LED
R2 105 IO_L01P_2/M1 11 12
IO_L11N_1 38 M0
R[0..2] R0 103 IO_L01N_2/M0 GS1 13 14
IO_L11P_1 62 SI SUSPEND GND
SW1 80 IO_2/MOSI/CSI_B SI GND
SW[1..6] IP_1/VREF_1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D 97 IP_1/VREF_1 D
100
106
118
128
137
17
26
34
56
65
81
89
9
GND
VCCINIT VCCAUX
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VCCINIT
VCCINIT
VCCIO
VCCIO
E E
VCCIO License : CC BY-SA
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF http://www.numato.com
Numato Lab
C2 C4 C6 C8 C9 C11 C29 C30
File: Spartan.sch
Sheet: /Spartan/
Title: Elbert - Spartan 3A FPGA Development Board
Size: A3 Date: 25 mar 2014 Rev:
KiCad E.D.A. Id: 2/5
1 2 3 4 5 6 7
1 2 3 4 5
VCCAUX
NOT POPULATED
A A
PWR_FLAG
10K
R1
C16
PIC18F14K50
0.1uF
VCCAUX 1 9 SI
22PF
VDD RC7/AN9/SDO/T1OSC0
8 AN0
C14
RC6/AN8/T13CKI/T1OSC1
5 PB
MCLK RC5/CCP1/P1A/T0CKI VCCAUX
6 AN2
MCLK
RC4/P1B/C12OUT/SRQ
NOT POPULATED
NOT POPULATED
CRYSTAL
7 AN1
12MHZ
MCLR 4 RC3/AN7/P1C/C12IN3/PGM
RA3/MCLR/VPP 14
Q1
3 RC2/AN6/P1D/C12IN2/CVREF/INT2
RA4/AN3/OSC2/CLKO 15 PROGB
2 RC1/AN5/C12IN1-/INT1/VREF- PROGB
RA5/OSC1/CLKI 16 DONE
C15
RC0/AN4/C12IN+/INT0/VREF+ DONE
10K
10K
R3
R4
19
D+/PGD
22PF
18 10 INITB
D-/PGC RB7/TX/CK INITB
11 SCK
17 RB6/SCK/SCL
D+ VUSB 12 CS
RB5/AN11/RX/DT
VSS
C17 13 SO
D- RB4/AN10/SDI/SDA
20
D+
D-
3
2
Shield_1
5
USB
X1
B SPI FLASH B
VCCAUX
Shield_2
USB
6
GND
Vbus
1
R39
R38
10k
10k
10k
R5
VUSB 0.1uF
VUSB
M25P16
C18
CS
CS 1 S VCC 8
1 MCLR
PIC ICSP
2 VCCAUX SO
SO 2 Q HOLD 7
3 GND
P9 3 W C 6 SCK
SCK
4 D+
5 D- GND 4 VSS D 5 SI
SI
6
U3
VCCAUX
VCCAUX
10K
R2
1 AN0
FWUP AN0
1 MCLR 2 AN1
AN1 P8 3 AN2
P10 AN2
C 2 GND
GND 4 GND C
License : CC BY-SA
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File: PIC.sch
Sheet: /PIC/
Title: Elbert - Spartan 3A FPGA Development Board
Size: A4 Date: 25 mar 2014 Rev:
KiCad E.D.A. Id: 3/5
1 2 3 4 5
1 2 3 4 5
A A
LM317 3.3V
EXTERNAL POWER
5V 3 IC5 2 VCCAUX
X1 IN OUT VCCAUX
+ 5V-EXT 1 C19 C22
C25
ADJ
P11
- GND 2 47uF 0.1uF
0.1uF
1
R8 R11
330E 220E
ADJ
VUSB
0.1uF 0.1uF
SJ7
1
R6 R9
330E 220E
B B
LM317 1.25V
R37 D10
5V 1 2 GND 5V 3 IC4 2 VCCINIT
1.5K IN OUT VCCINIT
C21 C24
POWER
ADJ
0.1uF 0.1uF
R7 1 R10
GND
10E 220E
C C
License : CC BY-SA
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File: Power Supply.sch
Sheet: /Power Supply/
Title: Elbert - Spartan 3A FPGA Development Board
Size: A4 Date: 25 mar 2014 Rev:
KiCad E.D.A. Id: 4/5
1 2 3 4 5
1 2 3 4 5 6 7
A A
VCCAUX
SEVEN SEGMENT DISPLAY PNP
C
VGA Connector
3
B
1
R20 J1 AFF1
Vsync 330R
Vsync 200R GND 8 7Seg_[0...7] Q2
E
2
8
7Seg_0 7 8 7 C.A.
R21 15 a 3
Hsync 6 C.A.
Hsync 200R 7 b
LED1 7 8 1 2 D1 7Seg_1 5 6 4
14 c
LED[1..8]
R27
R12
R31
2
1K
B0 6 d
LED2 5 6 1 2 D2 1K 7Seg_2 3 4 1
B[0...1] 13 e
RN1
2K2
R13 9
B1 Blue 5 f
LED3 3 4 1 2 D3 510R 7Seg_3 1 2 10 7Seg_1en
12 g 5
DP
4 VCCAUX
LED4 1 2 1 2 D4 R14 7Seg_4 7 8
PNP
C
11
3
G0 Green
2K 7SEGMENTS
G[0...2] 3 B
LED5 7 8 1 2 D5 R15 7Seg_5 5 6 1
G1 10 AFF2
R28
1K
2 Q3
E
2
B 8 B
LED6 5 6 1 2 D6 R16 7Seg_6 3 4 7 C.A.
G2 9 a 3
RN2
C.A.
2K2
510R 6
1 b
LED7 3 4 1 2 D7 7Seg_7 1 2 4
c
2
d
R32
1K
LED8 1 2 1 2 D8 R17 DB15 330R 1
e
R0 Red
GND 2K 9
R[0...2] f
R18 10
R1 g 5 7Seg_2en
1K DP
R19
VCCAUX
PNP
C
3
R2
510R 7SEGMENTS
B
1
AFF3
Q4
E
2
8
7 C.A.
a 3
6 C.A.
DIP SWITCH b
4
c
R33
2
1K
P7 d
DP[1..8] DP1 1 16 1
e
DP2 2 15 9
f
DP3 3 14 10
g
7Seg_3en
5
DP4 4 13 DP
DP5 5 12
DP6 6 11 7SEGMENTS
C C
DP7 7 10
DP8 8 9
GND
OFF
ON
MICROSD
R22
VCCAUX VCCAUX 100K
R23
100K
PUSH BUTTON SWITCH R24
100K AUDIO
R25
SW1 SW1 100K
SW[1..6]
R26 R29
100K 1 CON1
AUDIO_L 3.3K
2
SW2 SW2 MICRO_SD_N
DAT2
1 DAT2
3
R30
2 4
DAT3 DAT3 AUDIO_R 3.3K
3 5
CMD CMD GND
SW3 SW3 4 C28 C27
VCC 9
5 SHIELD AUDIO_JACK
CLK CLK 10
D GND 6 SHIELD 0.1uF 0.1uF D
GND 11
SW4 SW4 7 SHIELD
DAT0 DAT0 12 GND
SHIELD
C26 DAT1
8 DAT1
GND
SW5 SW5
U2
10uF
SW6 SW6
GND GND
E E
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File: Expansion Modules.sch
Sheet: /Expansion Modules/
Title: Elbert - Spartan 3A FPGA Development Board
Size: A3 Date: 25 mar 2014 Rev:
KiCad E.D.A. Id: 5/5
1 2 3 4 5 6 7