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Programacion avanzada

Matlab_simulink
System generator
Pspice
Verilog
Instalado_Proyect navegator
Vivalo

Reportes en Ingles
Internet de las cosas
Redes de sensores inalámbricos
Multiprocesos en un solo chip

Algotitmo de Hog
Transformada de Hough
Tarea 2 capitulos verilog HDL
Manual analizador ligico

HOW TO EXPORT Verilog HDL SIMULATION

DATA TO MATLAB?
Using Verilog HDL's file I/O capabilities, the simulation results of important
nodes in a DSP system can be written into a MATLAB file for more detailed
analysis. The simplified Verilog HDL code below shows how to generate
the MATLAB file:
?
module tb();
1
2
// I/Os:
3
wire [35:0] out;
4
reg [17:0] a, b;
5
reg clk;
6
7 // *** Local Integer Declarations ***
8 integer i_cnt;
9 integer m_file1; // File ID for Matlab File
10
11 // Instantiate UUT:
12 // dsp performs: out = a*b;
13 dsp uut (.clk (clk), .a (a), .b (b), .out (out));
14
15 // Generate clock:
always #1.65 clk <= ~clk;
16
17 // initial block
18 initial
19 begin
20 $timeformat(-9, 0, " ns", 8);
clk = 0;
21
a = 0;
22 b = 0;
23 i_cnt = 0;
24 @ (posedge clk);
25 m_file1=$fopen("sim_data.m");
$fdisplay(m_file1, "%%DSP Verilog HDL testbench results for Matlab Simulation.");
26 $fdisplay(m_file1, "%%This file contains the inputs of a and b, and the outputs out
27 $fwrite(m_file1, "\n");
28
29 $display("Capture 8192 samples of individual values for an 8192-point FFT.");
30 for (i_cnt=0;i_cnt<8192; i_cnt=i_cnt+1)
31 begin
a = i_cnt;
32 b = 1-i_cnt;
33 $fdisplay(m_file1,"a(%1.0d) = %1.0d;",i_cnt+1,$signed(a));
34 $fdisplay(m_file1,"b(%1.0d) = %1.0d;",i_cnt+1,$signed(b));
35 $fdisplay(m_file1,"out(%1.0d) = %1.0d;",i_cnt+1,$signed(out));
@ (posedge clk);
36 end
37
38 $fclose(m_file1);
39 $stop;
40 end
41
endmodule
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48
The Verilog HDL code generates a MATLAB file that contains the
multiplier a, the multiplicand b, and the product out. The values in
the MATLAB file are signed decimal values. The resulting file can now be
used in a MATLAB simulation.
?

1 %-------------------------------------------------------------------------------
%
2 % test_sim_data.m script
3 %
4 %-------------------------------------------------------------------------------
5 %
6 % My Company Confidential, Copyright 2017 Research and Development
%
7 %-------------------------------------------------------------------------------
8 %
9 % created on: 03/22/2017
10 % created by: jwwebb
% last edit on: $DateTime: $
11
% last edit by: $Author: $
12 % revision: $Revision: $
13 % comments: Generated
14 %
15 %-------------------------------------------------------------------------------
% Common IP
16 %
17 % This matlab script implements the plotting of various test points
18 % along the data path in the DSP Verilog HDL module.
19 %
20 %-------------------------------------------------------------------------------
%% Setup Environment
21 clear;clc;close all;
22 addpath('../data/hdl/');
23
24 %% Set Plotting Variables:
25 PlotOn = 1;
PrintOn = 0;
26
27 %% Load Data
28 sim_data;
29
30 %% Prepare X-Axis Data:
31 x=1:length(a);
32
33 %% Plot the Data:
if PlotOn
34 %% Plot Inputs and Outputs:
35 figure(1);
36 set(gca,'FontSize',14.0);
37 hold on;
plot(x,a,'r-s','LineWidth',2.0);
38 plot(x,b,'k-o','LineWidth',2.0);
39 plot(x,out,'b-^','LineWidth',2.0);
40 title('Multiplier I/O','FontSize',14.0);
41 axis([x(1) x(end) min(out)-1 max(out)+1]);
42 grid on;
hold off;
43 % Save plot:
44 if PrintOn
45 png_file = sprintf('../images/hdl/multiplier_io.png');
46 print(png_file, '-dpng');
eps_file = sprintf('../images/hdl/multiplier_io.eps');
47 print(eps_file, '-depsc');
48 end
49 end
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HOW TO EXPORT MATLAB MODEL DATA

TO Verilog HDL?

Likewise, MATLAB can be used to generate a Verilog HDL file by using its
file I/O capabilities. The MATLAB code used to generate a Verilog HDL file is
shown below:
?
%-------------------------------------------------------------------------------
1 %
2 % test_sim_data.m script
3 %
4 %-------------------------------------------------------------------------------
%
5 % My Company Confidential, Copyright 2017 Research and Development
6 %
7 %-------------------------------------------------------------------------------
8 %
% created on: 03/22/2017
9 % created by: jwwebb
10 % last edit on: $DateTime: $
11 % last edit by: $Author: $
12 % revision: $Revision: $
13 % comments: Generated
%
14 %-------------------------------------------------------------------------------
15 % Common IP
16 %
17 % This matlab script generates data for use in a Verilog HDL simulation.
%
18 %-------------------------------------------------------------------------------
19 %% Setup Environment
20 clear;clc;close all;
21
22 %% Set Variables:
23 PlotOn = 1;
PrintOn = 0;
24 WriteMe = 1;
25
26 %% Generate impulse response stimulus vector for Verilog HDL simulation:
27 %--------------------------------------------------------------
28 % Write the Verilog HDL File:
29 %--------------------------------------------------------------
if WriteMe
30 %----------------------------------------------------------
31 % Open the File Handle:
32 %----------------------------------------------------------
33 filename = sprintf('./stim.v');
fid = fopen(filename,'w');
34 %----------------------------------------------------------
35 % Write the File Header:
36 %----------------------------------------------------------
37 fprintf(fid,'module stim (input wire [9:0] addr,\n');
38 fprintf(fid,' input wire clk,\n');
fprintf(fid,' input wire rst_n,\n');
39 fprintf(fid,' output wire [17:0] s_data);\n');
40 fprintf(fid,'\n\n');
41 fprintf(fid,'wire [17:0] data_rom [50:0];\n\n');
42 %----------------------------------------------------------
% Write the File Data:
43 %----------------------------------------------------------
44 fprintf(fid,'assign data_rom[0] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1.0f%1.
45 %1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f;
46 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
47
48 data3 = zeros(1,100);
49
50 for k=1:15,
51 fprintf(fid,'assign data_rom[%1.0f] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_..
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1
52 %1.0f%1.0f%1.0f%1.0f;\n',k,data3(k),da
53 data3(k),data3(k),data3(k),data3(k),da
54 data3(k),data3(k),data3(k),data3(k),da
55 data3(k),data3(k),data3(k),data3(k),da
end
56
57 fprintf(fid,'assign data_rom[16] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1.0f%1
58 %1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f
59 0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
60
61 for k=17:50,
62 fprintf(fid,'assign data_rom[%1.0f] = 18''b%1.0f%1.0f_%1.0f%1.0f%1.0f%1.0f_%1
%1.0f%1.0f%1.0f%1.0f_%1.0f%1.0f%1.0f%1
63 data3(k),data3(k),data3(k),data3(k),da
64 data3(k),data3(k),data3(k),data3(k),da
65 data3(k),data3(k),data3(k),data3(k),da
66 end
67
fprintf(fid,'\n\n');
68 fprintf(fid,'//always @ (posedge clk or negedge rst_n)\n');
69 fprintf(fid,'//begin\n');
70 fprintf(fid,'\t//if (!rst_n)\n');
71 fprintf(fid,'\t\t//s_data[17:0] <= 18''h00000;\n');
72 fprintf(fid,'\t//else\n');
fprintf(fid,'\t\t//s_data[17:0] <= data_rom[addr];\n');
73 fprintf(fid,'//end\n');
74
75 fprintf(fid,'\tassign s_data[17:0] = data_rom[addr];\n');
76
77 fprintf(fid,'\nendmodule\n');
78 %----------------------------------------------------------
79 % Close the File Handle
%----------------------------------------------------------
80 fclose(fid);
81 end
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97
The MATLAB code generates a Verilog HDL file containing a ROM with two
impulse functions. This ROM can be used to stimulate a FIR filter in
ModelSim to verify that the filter coefficients are output in the correct order
and value. The Verilog HDL module can be instantiated in the Verilog HDL
test bench of the unit under test (UUT).