STA vs DTA

Why do we normally do Static Timing Analysis and not

Dynamic Timing Analysis? What is the difference between
them?
Timing Analysis can be done in both ways; static as well as dynamic. Dynamic Timing
analysis requires a comprehensive set of input vectors to check the timing characteristics of
the paths in the design. Basically it determines the full behavior of the circuit for a given set
of input vectors. Dynamic simulation can verify the functionality of the design as well as
timing requirements. For example if we have 100 inputs then we need to do 2 to the power
of 100 simulations to complete the analysis. The amount of analysis is astronomical
compared to static analysis.Static Timing analysis checks every path in the design for timing
violations without checking the functionality of the design. This way, one can do timing and
functional analysis same time but separately. This is faster than dynamic timing simulation
because there is no need to generate any kind of test vectors. That’s why STA is the most
popular way of doing timing analysis

Dynamic Vs Static STA

Virtual Clock
virtual clock as the name suggests doesn't exist physically in the design at all, its just used for
the specifying the input / output delay values ( if no clock is existing )
virtual clock can be created same as Create_clock , except that the port/pin name must not be
specified !
incase if u have a purely combination path and if u want to specify a set_input_delay or a
set_output_delay for that path, then the virtual clock is used
Unateness
Unateness
A function is said to be unate if the rise transition on the positive unate input variable causes the ouput to
rise or no change and vice versa.

Negative unateness means cell output logic is inverted version of input logic. eg. In inverter having input
A and output Y, Y is -ve unate w.r.to A. Positive unate means cell output logic is same as that of input.
These +ve ad -ve unateness are constraints defined in library file and are defined for output pin w.r.to
some input pin.

A clock signal is positive unate if a rising edge at the clock source can only cause a rising edge at the
register clock pin, and a falling edge at the clock source can only cause a falling edge at the register clock
pin.

A clock signal is negative unate• if a rising edge at the clock source can only cause a falling edge at the
register clock pin, and a falling edge at the clock source can only cause a rising edge at the register clock
pin. In other words, the clock signal is inverted.

A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in the
clock path. For example, a clock that passes through an XOR gate is not unate because there are
nonunate arcs in the gate. The clock sense could be either positive or negative, depending on the state of
the other input to the XOR gate.

Jitter
Jitter
The short-term variations of a signal with respect to its ideal position in time.
Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter value.
From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry.
This can be modeled by adding uncertainty regions around the rising and falling edges of the clock
waveform.

Sources of Jitter Common sources of jitter include:

Internal circuitry of the phase-locked loop (PLL)

Random thermal noise from a crystal
Other resonating devices
Random mechanical noise from crystal vibration
Signal transmitters
Traces and cables
Connectors
Receivers