KKKL2173

Analogue Electronics

Chp. 7: FET Biasing

Rosmina Jaafar
 General Relationships
 For ALL FETs: IG  0 A I D  I S
2
 VGS 
 For JFETs and D-MOSFETs: I D  I DSS 1  
 VP 

 For E-MOSFETs: I D  k (VGS  VT ) 2

 BJT : linear relationship between IB and IC

 FET : non-linear relationship between VGS and ID

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 Common FET Biasing Circuits
• JFET
Fixed Bias
Self Bias
Voltage Divider Bias

• D-MOSFET
Self Bias
Voltage Divider Bias

• E-MOSFET
Voltage Divider Bias
Feedback Bias
3
JFET BIASING CIRCUITS

4
 Fixed-Bias JFET
 The simplest of biasing arrangements

IG  0 A
ID  IS
2
 VGS 
I D  I DSS 1  
 VP 

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 Fixed-Bias JFET
 The simplest of biasing arrangements
 Can be solved using either mathematical or graphical
approach Mathematical Graphical
Approach Approach

VGS  VGG
VDS  VDD  I D RD
VS  0
VD  VDS
VG  VGS
2
 V 
I D  I DSS 1  GS 
 VP 
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 Fixed Bias JFET: Example 7.1
 Determine the following for the network below
 VGSQ  V 
2

I D  I DSS 1  GS 
 IDQ  VP 
 VDS
 VG
 VS

 Answers:

VGSQ  VGG  2V I DQ  5.625mA

VDS  4.75V VG  2V VS  0V
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Fixed Bias JFET: Example – graphical method
2
 VGS 
VGSQ  VGG  2V I D  I DSS 1  
 VP 
I DQ  5.625mA
VGS  VGG
VDS  4.75V
VG  2V VDS  VDD  I D RD
VS  0V VG  VGS
VGS ID VS  0
0 IDSS
0.3VP 0.5IDSS
0.5VP 0.25IDSS
VP 0

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 Self Bias JFET
 Self-bias eliminates the need for 2 dc supplies

IG  0 A
ID  IS
2
 VGS 
I D  I DSS 1  
 VP 

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 Self Bias JFET
 Can be solved using either mathematical or graphical
approach

VGS   I D RS

VDS  VDD  I D ( RD  RS )

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 Self Bias JFET
 Graphical Approach (to find VGSQ and IDQ) :
 Plot the transfer curve using IDSS and VP using shorthand method.

 Plot VGS   I D RS using the component value for RS.

 The Q-point is located where the first line intersects the transfer
curve.

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 Self Bias JFET: Example 7.2
 Determine the following for the network below
 VGSQ
 IDQ
 VDS
 VS
 VG
VDS  VDD  I D ( RD  RS )
 VD

 Answers:
VGSQ  2.6V I DQ  2.6mA

VS  2.6V VG  0V

VD  11.42V VDS  8.82V

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Self Bias JFET: Example 7.2
• Plot ID and VGS and draw a line from the
origin of the axis.

VGS  ID RS  ID (1000)



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Self Bias JFET: Example 7.2
• Plot the transfer curve using IDSS and VP
using shorthand method.

VGS ID
0 IDSS
0.3VP 0.5IDSS
0.5VP 0.25IDSS
VP 0

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Self Bias JFET: Example 7.2
 Superimpose the load line on
top of the transfer curve

VDS  VDD  I D ( RD  RS )

VS  I D RS VGSQ  2.6V

VG  0V I DQ  2.6mA
VDS  8.82V
VD  VDS  VS
VS  2.6V
VG  0V
VD  11.42V
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 JFET: voltage divider bias
 Basic construction is same as BJT except that IG = 0 A.

IG  0A
ID  IS
2
 VGS 
I D  I DSS 1  
 VP 

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 JFET Voltage Divider Bias
 VG is equal to voltage across divider resistor R2:
R 2 VDD
VG 
R1  R 2

 Using Kirchhoff’s Voltage Law:

VGS  VG  I D RS

VDS  VDD  I D ( RD  RS )

VDD
I R1  I R2 
R1  R 2

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 JFET Voltage Divider Bias
 Graphical Approach (to find VGSQ and IDQ) :
 Plot a line for:
 VGS = VG when ID = 0 A VGS  VG  I D RS
 VGS = 0 V when ID = VG/RS
 Plot the transfer curve using IDSS and VP using shorthand method.
 The Q-point is located at the intersection.

VGS  VG  I D RS
VGS ID
0 IDSS
0.3VP 0.5IDSS
0.5VP 0.25IDSS
VP 0

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 JFET Voltage Divider Bias: Example 7.4
 Determine the following for the network below
 IDQ and VGSQ
 VD
 VS
 VDS
 VDG
 Answers:

R 2 VDD VGS  VG  I D RS
VG 
R1  R 2 V  V  I ( R  R )
DS DD D D S

VGSQ  1.8V I DQ  2.4mA VD  10.24V

VS  3.6V VDS  6.64V VDG  8.42V

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 JFET voltage Divider Bias: Example 7.4
 Plot a line for:
 VGS = VG at ID = 0A
 VGS = 0V at ID = VG/RS
VGS  VG  I D RS
 Plot the transfer curve using IDSS and VP
and shorthand method.
 Identify the Q-point.

R 2 VDD
VG 
R1  R 2
VGSQ  1.8V
VD  VDD  I D RD
I DQ  2.4mA
VS  I D RS
VD  10.24V
VDS  VDD  I D ( RD  RS )
VS  3.6V
VDS  VD  VS
VDS  6.64V
VDG  VD  VG VDG  8.42V
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D-MOSFET BIASING CIRCUITS

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 D-MOSFET Self Bias
 D-MOSFET bias circuits are similar to JFETs.
 The only difference is that D-MOSFETs can operate with
positive values of VGS and with ID values that exceed
IDSS.

IG  0A
ID  IS
2
 VGS 
I D  I DSS 1  
 VP 

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 D-MOSFET Self Bias
 Graphical Approach (to find VGSQ and IDQ) :
 Plot the transfer curve using IDSS and VP using shorthand method.
 Plot ID vs VGS using VGS   I D RS 2
 VGS 
 Take a positive value of VGS and find the ID value using I D  I DSS 1  
 The Q-point is located at the intersection point  VP 

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 D-MOSFET self bias: Example 7.8
 Determine the following for the network below
 IDQ and VGSQ
 VD

 Answers:

VGSQ  4.3V
I DQ  1.7mA

VD  9.46V

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 D-MOSFET: Example 7.8
 Plot the transfer curve using shorthand method.
 Take a positive value of VGS and find the ID value
using: 2
 V 
I D  I DSS 1  GS 
 VP 
 Plot ID vs VGS using VGS   I D RS
 Identify the intersection is Q-point
2
 V 
I D  I DSS 1  GS 
 VP 

VGS
ID  
RS
VD  VDD  I D RD
VGSQ  4.3V
I DQ  1.7mA
VD  9.46V
 D-MOSFET voltage divider bias
 D-MOSFET bias circuits are similar to JFETs

I D  I S IG  0A
2
 VGS 
I D  I DSS 1  
 VP 

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 D-MOSFET Voltage Divider Bias
 Plot the transfer curve using IDSS and VP using shorthand method.
2
 Take a positive value of VGS and find the ID value using I  I 1  VGS 
D DSS  
 VP 
 Plot ID vs VGS VGS  VG  I D RS
 The Q-point is the intersection point.

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E-MOSFET BIASING CIRCUITS

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 E-MOSFET voltage divider bias
 E-MOSFETs use the same procedure to JFETs and D-
MOSFETs

R 2 VDD
VG 
R1  R 2

VGS  VG  I D RS

VDS  VDD  I D ( RD  RS )

I D  k (VGS  VT ) 2

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 E-MOSFET voltage divider bias
 Graphical Approach: k
I D ( on)
 Calculate the value for k (VGS ( on)  VGS (th ) ) 2
 Plot VGS vs ID using
I D  k (VGS  VT ) 2
 Plot for:
 VGS = VG at ID = 0A
 VGS = 0V at ID = VG/RS
VGS  VG  I D RS
 Identify the Q-point

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 E-MOSFET voltage divider:
Example 7.11
 Determine the following for the network below
 IDQ and VGSQ
 VD

 Answers:

VGSQ  12.5V
I DQ  6.7mA

VDS  14.4V

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 E-MOSFET voltage divider bias: Example 7.11
I D ( on)
• Calculate the value for k, k
(VGS ( on)  VGS (th ) ) 2

• Plot VGS vs ID for the range of interest I D  k (VGS  VT ) 2

• Plot VGS  VG  I D RS
• Identify the Q-point

VGSQ  12.5V
I DQ  6.7mA

VDS  VDD  I D ( RD  RS )

VDS  14.4V
R 2 VDD
VG 
R1  R 2
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 E-MOSFET Feedback Bias

IG  0 A, VRG  0V

VGS  VDS

VGS  VDD  I D RD

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 E-MOSFET Feedback Bias
I D ( on)
 Graphical Approach (to find VGSQ and IDQ) : k
(VGS ( on)  VGS (th ) ) 2
 Calculate the value for k
 Plot VGS vs ID for the range of interest.
 Plot VGS  VDD  I D RD
 Identify the Q-point
I D  k (VGS  VT ) 2

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 E-MOSFET feedback bias:
Example 7.10
 Determine the following for the network below
 IDQ and VGSQ

 Answers:

VGSQ  6.4V
I DQ  2.75mA

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 E-MOSFET feedback bias: Example 7.10
• Calculate the value for k, I D ( on)
k
(VGS ( on)  VGS (th ) ) 2
• Plot VGS vs ID for the range of interest
I D  k (VGS  VT ) 2
• Plot
VGS  VDD  I D RD

• Identify the Q-point

VGSQ  6.4V
I DQ  2.75mA

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 p-Channel FETs
 For p-channel FETs the same calculations and graphs
are used, except that the voltage polarities and current
directions are the opposite
 The graphs will be mirrors of the n-channel graphs

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 Practical Applications
 Voltage-controlled resistor
 Idea: control the RDS using VGS
 JFET voltmeter
 Idea: control the RDS using VGS
 Timer network
 Idea: control the ID using VGS
 Fiber optic circuitry
 Idea: control the VD using VGS
 MOSFET relay driver
 Idea: control the ID using VGS

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 Practical Applications
MOSFET relay driver
 To drive high-cuurrent/high-voltage systems without drawing power from the
driving circuit.
 Variable resistance of the photocell modulates ID , driving the relay.

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FET biasing tutorial assignment

Solve the following Chap. 7 problems:

1, 6, 12, 20, 22

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