INCISIVE VERIFICATION ARTICLE
JUNE 2005
IEEE P1647 E LANGUAGE: CADENCE PLANS FOR STANDARDIZATION AND INTEGRATION
IN INCISIVE VERIFICATION FLOW
VICTOR BERMAN, CADENCE DESIGN SYSTEMS
INTRODUCTION
Now that the acquisition of Verisity by Cadence has
been completed, Cadence can begin to communicate
the plans for the integration of the new technology
into the Cadence® Incisive™ advanced verification
flow. The newly formed Cadence Verification Division
will be the focus for integrating the Verisity
verification process automation (VPA) technologies,
IP, and methodologies with the Incisive functional
verification platform.
Cadence will continue its support for and leadership
in driving open standards with strong backing for the
IEEE P1647 e Working Group. Cadence is fully behind
an open and IEEE standard e language and will
provide the industry’s ONLY fully integrated e,
SystemC®, and SystemVerilog solution!
We are continuing — and expanding — our multi-
language, open-standard approach to design and
verification. Below is our brief summary of the
primary utilization of supported languages:
• SystemC for systems designers to model architecture
• SCV open-source, roll-your-own verification
• Verilog®, VHDL, and SystemVerilog for designers to
model the design
• e for verification specialists and “plan-to-closure”
verification process automation
• SystemVerilog testbench to extend the designer’s
contribution to verification
• SVA and PSL for designers and verification specialists
to model assertions
Of course, your views on language utilization
may be different from ours, depending on your
specific requirements. That is why we provide a
comprehensive, integrated platform for efficient
implementation of essentially any design and
verification flow.
E IN THE CONTEXT OF VERIFICATION
PROCESS AUTOMATION
So, how does e fit into the Cadence verification
landscape? Everyone is by now familiar with the
problem of increased demands on verification caused
by chip complexity and time-to-market pressures.
To cope with these demands, chip designers and
therefore the EDA industry have moved to the use
of specialized languages — and software supporting
these languages — to improve the efficiency of the
verification process. In the case of e, the founders of
Verisity wanted to create an “extendable” and
“English-like” verification language independent
from hardware and software. When coupled with the
VPA technology, methodologies, and verification IP
(VIP), e enables users to span and reuse block-, chip-,
and system-level verification, and to support
traceable metrics for project-level verification
management.
As seen in the above language-utilization map, the
vertical role of e is complementary to the more
horizontal roles of SystemC and SystemVerilog for
system and logic designers.
E AND THE IEEE P1647 E WORKING Cadence will provide additional information about
the unique features of the e language and its
GROUP
application to verification in subsequent issues of
For more than ten years, the e language has been this newsletter, as well as in our seminars and other
under continuous development by Verisity Design, tutorial formats. You may also refer to the paper
Inc., which is now a key part of the Cadence on e and aspect-oriented programming in the article
Verification Division. It is linked explicitly to an “The e Language: A Fresh Separation of Concerns,”
extensive set of technologies, methodologies, and IP by Yoav Hollander, Matthew Morley, and Amos Noy,
that are referred to collectively as verification process which will be available on the Cadence website.
automation (VPA). As such, e was and continues to be
driven by the world’s leading-edge customers in the
context of applying the most advanced, highly
E IN THE MULTI-LANGUAGE FLOW
automated and reusable processes. Therefore, it was e is designed to co-exist in a tightly coupled
not driven purely from a language point of view. This relationship to design languages such as Verilog,
fact enabled the overall VPA solutions to be far more SystemVerilog, VHDL, and SystemC through well-
effective in creating predictability, productivity, and specified interfaces where the semantics of data
system-level quality. crossing the boundary are defined. The underlying
semantics of the verification and design languages
e [1,2] can be characterized generally as an
remain distinct but with well-defined interactions
imperative, object-oriented (OO) language with
between them.
concurrency, the ability to generate constrained
random values, with mechanisms for checking Extensive industry use of this paradigm has shown
functional coverage, and a way to check temporal that it is an extremely effective methodology for
properties (assertions). However, e goes beyond the advanced verification. More than
traditional OO capabilities with the addition of 40 million lines of e code are in production use by
aspect-oriented programming. This enables the the world’s largest semiconductor, systems, and IP
development of orthogonal aspects as a way of companies. There have been thousands of successful
rapidly creating and extending complex models and tapeouts using e and the Versity VPA solutions. A
of enabling reuse across multiple applications and large percentage of these designs were done using
abstractions. The orthogonal relationship between combined Verisity/Cadence flows even before the
objects and aspects enables the separation of merger occurred. This is one of the strong reasons
concerns that is key to cutting through the that we are completely confident that the combined
complexities in verifying a system and to reusing Verisity/Cadence solutions will effectively meet the
verification environments. needs of our customers — because it already has.
e also adds dynamic (“when”) inheritance, facilitating
configuration or adaptation of code without intrusive
changes. e is a hierarchical constraint language,
enabling easy adaptation of environments for
particular configuration and test needs, again
without intrusive change. It provides a unique [1] Samir Palnitkar, Design Verification with e.
mechanism for combining imperative and declarative Prentice Hall, Upper Saddle River, New Jersey, 2003.
constructs to model concurrency and temporal
aspects. [2] Stephen A. Edwards, Design and Verification
Languages. Department of Computer Science
In June 2002, Verisity announced its intention to Columbia University, New York, November, 2004.
make the language public and begin an IEEE
standardization project. Under the sponsorship of [3] Sason Iman and Sunita Joshi, The e-Hardware
the Computer Society Design Automation Standards Verificaiton Language. Springer, May 28, 2004.
Committee (IEEE CS-DASC), a PAR for the work was
prepared and approved by NesCom in June 2003.
The working group is organized with individual
rather than entity membership, and the planned
ballot will also be by individual vote. Currently there
are about 200 members of the working group with
about 25 active voting members. It is expected that
final draft standard will be available early in the third
quarter of 2005 and will go to ballot in September
2005. Extensive documentation for the standard is
available now on the IEEE P1647 website. For details
visit www.ieee1647.org.

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