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Library IEEE
PRACTICA 2: MULTIPLEXACION
AUXILIAR: DAVID BARRIENTOS
CODIGO EN VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity practica2 is
Port(
CLK : in STD_LOGIC;
);
end practica2;
begin
process (CLK)
begin
if(rising_edge(clk)) then
case Estado is
if (contador2=11999999) then
contador2<=0;
if (segundo=9) then
Estado<= minutos;
else
segundo<=segundo+1;
end if;
else
end if;
if (decena=5) then
Estado<= unidad;
else
decena<=decena+1;
segundo<=0;
Estado<= segundos;
end if;
if (minuto=9) then
Estado<= inicio;
else
minuto<=minuto+1;
decena<=0;
Estado<= segundos;
end if;
decena<=0;
segundo<=0;
contador2<=0;
minuto<=0;
estado<=segundos;
decena<= 0;
segundo<= 0;
contador2<=0;
minuto<=0;
end case;
end if;
end process;
PROCESS(CLK)
begin
if (rising_edge(CLK) ) then
if (contador=99999) then
contador <=0;
else
end if;
Case numero is
End case;
EN<="110";
numero<=segundo;
EN<="101";
numero<=decena;
EN<="011";
numero<=minuto;
end if;
end if;
end process;
end Behavioral;
UCF
# # Clock 12 MHz
################################################################################
#####################
#"SevenSegment[7]"
NET "SSD[0]" LOC = P117 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[1]" LOC = P116 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[2]" LOC = P115 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[3]" LOC = P113 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[4]" LOC = P112 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[5]" LOC = P111 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[6]" LOC = P110 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "SSD[7]" LOC = P114 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "EN[2]" LOC = P124 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "EN[1]" LOC = P121 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;
NET "EN[0]" LOC = P120 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;