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Handbook of Interconnect Theory and Design Practices. Wiley. New York 2000
Handbook of Interconnect Theory and Design Practices. Wiley. New York 2000
Handbook of Interconnect Theory and Design Practices. Wiley. New York 2000
Simulation with a SystemC model of the hardware. This allows for a very early start of firmware
development without any access to hardware and allows to test the functionality of the code
assuming the model is accurate. The main limitations are lack of system view and (depending on
the model accuracy) lack of hardware timing accuracy (behavioral models)
Stollon, D. N., Leatherman, R., Ableidinger, B.: Multi-Core Embedded Debug for Structured
ASIC Systems. In: Proceedings of DesignCon 2004. Feb. 2004