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Advanced Topics in EMC Design
Advanced Topics in EMC Design
Advanced Topics in EMC Design
Tim Williams
Elmac Services
1
The purpose of the ground plane
via connections directly to ground plane
ground plane
power plane
side view
connections to ground plane minimise total loop area for each track
element
inductance LG
di/dt
VN
circulating currents di/dt
in ground plane
VN = -LG · di/dt
total noise voltage = ΣVN
2
The effect of a discontinuity in Iret
Iret
Iret
Iret
Iret
VN
generates noise across radiating dipole
Advice to split
Example
3
Why separate A & D ground planes?
ADC
analogue & digital currents
kept separate, but...
4
Multiple A-D devices
Thinks: how
From Analog useful is this
Devices
Engineering
advice?
Note EE-28
ADC1
ADC3
10
5
Multiple A-D packages: several links
ADC2
digital … but, will they, and,
plane noise how badly?
voltages
… and anyway,
ADC3 implementing multiple links
is nearly all the way to a full
ground plane … so why
have splits at all?
11
each analogue
digital noise circuit carefully
currents ADC1 grouped
both AGND and
DGND connected to
common GP
12
6
So why ...
chip
Internal AGND
remains unaffected
by digital noise
High digital ∆Ι
ground current
Little or no analogue
∆Ι ground current
Bond wires add
ground inductance
package
DGND AGND
13
10Ω
3cm L x 0.5mm W track * 5cm wide ground
plane at 0.8mm under
1Ω finite ground plane * 3cm length of track
100mΩ
ohms per square of
infinite plane
10mΩ
1-oz Cu plane
1mΩ
0.1 1.0 MHz 10 100 1G
14
7
Issue 2: Digital decoupling
Outline
• The purpose of decoupling
• Capacitor selection and layout
• Paralleling capacitors
• The planes as a transmission line
• Resistive damping
• Segmenting the power plane with inductors
15
16
8
Decoupling regime vs frequency
LT LP
LC LC +
CBULK -
CD CD
17
ground connection
inductance
18
9
SM capacitor impedances (1)
19
H (mils) L (pH)
1000 NPO
20 300
H X7R
mΩ
30 450
Ω
40 600
50 700 500
Link to
4 Murata
capacitor
3 data
Progression of decoupling
1
capacitor pad and via layout
nH
years
20
10
Capacitor value
Capacitor self resonance
40.0
30.0
20.0
10.0
100nF 10nH
dB ohms
21
L1 L2 L3 L4
ZPLANE C1 C2 C3 C4 CBULK
CPLANE
RIC
R1 R2 R3 R4
effect of CBULK
Modelled with:
ZPLANE C1 - 4 = 22nF
dBΩ L1 = 1nH, L2 = 2nH, L3 = 3nH, L4 = 4nH
CBULK = 1µF, L = 15nH, R = 0.1Ω
RIC = 50Ω
CPLANE = 3nF
effect of C1 - 4
22
11
Parallel capacitors
dBΩ
• 2 capacitors of
different values at 47nF // 1µF
one point are
dangerous
• Multiple capacitors
of the same value
9 x 22nF, 2nH
with power/ground
planes are useful
23
• The previous model assumed the board was small with respect to a wavelength (< λ/10)
I
n=1
n=2
VCC
24
12
Transmission line impedance
W h
h Z0, h = 800
Z0 = 120 · π ·
5
C, h = 50
√εr · W 1
C, h = 200
4
C, h = 800
Z0 Ω
A (cm2) 3
C nF
C (pF) = 0.0885 ·
0.1 2
h (cm)
1
25
26
13
Segmenting the power plane
ground plane
3V3 plane B
3V3 plane C
3V3 plane A
1V8 plane
3V3 plane D
• splitting the power plane(s) (not the ground plane) into several
segments, each decoupled by a choke, creates “islands” for noisy
or sensitive circuits and reduces the impact of plane resonances
27
Conclusions
28
14
Issue 3: Mode conversion
in interface filters
Outline
29
Input amplifier
Input cable
30
15
Typical filter circuit
Input amplifier
Common-mode choke
Input terminals
3-terminal
capacitors to Input 0V
chassis capacitors
to 0V
chassis ground
31
CM choke
Input 3-T caps
Injection CDN to chassis Input
impedance VDM
Source
DM
impedance
VCM
Input caps
to 0V
VIN
32
16
Conversion from CM to DM
33
Modelling
34
17
Model results: initial assumptions
Near-perfect balance
0
-40
-60
dB VDM/VIN
-80
-100
-140
1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08
35
-40
-60
dB
Unbalance in 1000pF input caps C5, C6
-80
36
18
Model results: real life
-40
-60
dB
-80
-140
1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08
37
-40
-60
dB
-80
-140
1.00E+05 1.00E+06 Hz 1.00E+07 1.00E+08
38
19
Conclusions
39
End
Thanks for your attention!
20